參數(shù)資料
型號(hào): MAX9152ESE+
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 10/12頁(yè)
文件大小: 0K
描述: IC CROSSPOINT SWITCH 2X2 16SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 50
功能: 交叉點(diǎn)開關(guān)
電路: 1 x 2:2
電壓電源: 單電源
電壓 - 電源,單路/雙路(±): 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC
包裝: 管件
Input Fail-Safe
The differential inputs of the MAX9152 do not have
internal fail-safe biasing. If fail-safe biasing is required,
it can be implemented with external large-value resis-
tors. IN_+ should be pulled up to VCC with 10k
and
IN_ should be pulled down to GND with 10k
. The volt-
age-divider formed by the 10k
resistors and the 100
termination resistor (across IN_+ and IN_-) provides a
slight positive differential bias and sets a high state at
the device output when inputs are undriven.
Output Resistance
The MAX9152 has a selectable differential output resis-
tance to reduce reflections from impedance discontinu-
ities in the interconnect. Reflections are reduced,
compared to a high-impedance output. A termination
resistor at the receiver is still required and is the primary
termination for the interconnect. Select the output resis-
tance that best matches the differential characteristic
impedance of the interconnect used.
Select Function
The SEL0 and SEL1 logic inputs allow the device to be
configured as a high-speed differential crosspoint, 2:1
mux, 1:2 demux, dual repeater, or 1:2 splitter (Figure
8). See Table 1 for mode selection settings.
Enable Function
The EN0 and EN1 logic inputs enable and disable dri-
ver outputs OUT0 and OUT1. Setting EN0 or EN1 high
enables the corresponding driver output. Setting EN0
MAX9152
800Mbps LVDS/LVPECL-to-LVDS 2 x 2
Crosspoint Switch
_______________________________________________________________________________________
7
1.5V
EN0 = EN1 = HIGH
VID = (VIN_+)
(VIN_-)
tHOLD
tSWITCH
tSET
VID = 0
IN1
IN0
IN0+
IN0-
IN1-
IN1+
OUT_-
SEL_
OUT_+
1.5V
EN0 = EN1 = HIGH
VID = (VIN_+)
(VIN_-)
tHOLD
tSWITCH
tSET
VID = 0
IN0
IN1
IN0+
IN0-
IN1-
IN1+
OUT_+
SEL_
OUT_-
Figure 2. Input to Rising Edge Select Setup, Hold, and Mux Switch Timing Diagram
Figure 3. Input to Falling Edge Select Setup, Hold, and Mux Switch Timing Diagram
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