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參數(shù)資料
| 型號(hào)： | MAX9115EXK-T |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Single LVDS Line Receiver in SC70 |
| 中文描述： | LINE RECEIVER, PDSO5 |
| 封裝： | SC-70, 5 PIN |
| 文件頁(yè)數(shù)： | 7/8頁(yè) |
| 文件大?。?/td> | 139K |
| 代理商： | MAX9115EXK-T |
Differential Traces
Input trace characteristics affect the performance of the
MAX9115. Use controlled-impedance PC board traces,
typically 100
. Match the termination resistor to this
characteristic impedance.
Eliminate reflections and ensure that noise couples as
common mode by running the differential traces close
together. Reduce skew by matching the electrical
length of the traces. Excessive skew can result in a
degradation of magnetic field cancellation.
Input differential signals should be routed close to each
other to cancel their external magnetic field. Maintain a
constant distance between the differential traces to
avoid discontinuities in differential impedance. Minimize
the number of vias to further prevent impedance dis-
continuities.
Cables and Connectors
Transmission media should typically have a controlled
differential impedance of 100
. Use cables and con-
nectors that have matched differential impedance to
minimize impedance discontinuities.
Avoid the use of unbalanced cables such as ribbon or
simple coaxial cable. Balanced cables such as twisted
pair offer superior signal quality and tend to generate
less EMI due to canceling effects. Balanced cables
tend to pick up noise as common mode, which is
rejected by the LVDS receiver.
Termination
The MAX9115 requires an external termination resistor.
The termination resistor should match the differential
impedance of the transmission line. Termination resis-
tance is typically 100
but may range between 90
to
132
, depending on the characteristic impedance of
the transmission medium.
When using the MAX9115, minimize the distance
between the input termination resistor and the MAX9115
receiver inputs. Use 1% surface-mount resistors.
Board Layout
For LVDS applications, a four-layer PC board that pro-
vides separate layers, power, ground, and input/output
signals is recommended. Keep the LVDS input signals
away from the output LVCMOS/LVTTL signal to prevent
coupling (Figure 4). To minimize crosstalk, do not run
the output in parallel with the inputs. Extend the ground
pin trace under the package to the other side between
IN+ and OUT to provide isolation between IN+ and
OUT.
Chip Information
TRANSISTOR COUNT: 201
PROCESS: CMOS
M
Single LVDS Line Receiver in SC70
_______________________________________________________________________________________
7
20%
20%
50%
50%
80%
COMMON-MODE VOLTAGE: V
= (V
IN+
+ V
) / 2
DIFFERENTIAL INPUT VOLTAGE: V
ID
= (V
IN+
) - (V
IN-
)
80%
V
OH
V
OL
t
TLH
t
THL
V
OUT
V
ID
= 0
V
ID
= 0
V
ID
V
IN-
V
IN+
t
PLHD
t
PHLD
Figure 3. Propagation Delay and Transition-Time Waveforms
U1
R1
U1: MAX9115
R1, C1 ARE 0402 TYPE
C1
0.01
μ
F
IN-
GND
(LVDS INPUTS)
(LVTTL/LVCMOS OUTPUT)
V
CC
OUT
IN+
Figure 4. Board Layout
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