參數(shù)資料
型號: MAX8896EREE+T
廠商: Maxim Integrated
文件頁數(shù): 10/17頁
文件大?。?/td> 449K
描述: IC REG TRPL BCK/LINEAR 16UCSP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1
拓撲: 降壓(降壓)同步(2),線性(LDO)(1)
功能: 任何功能
輸出數(shù): 3
頻率 - 開關(guān): 2MHz
電壓/電流 - 輸出 1: 0.2 V ~ 1.7 V,700mA
電壓/電流 - 輸出 2: 3.1V,200mA
電壓/電流 - 輸出 3: 2.8V,200mA
帶 LED 驅(qū)動器:
帶監(jiān)控器:
帶序列發(fā)生器:
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-WFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 16-UCSP(4x4)
包裝: 標準包裝
其它名稱: MAX8896EREE+TDKR
Dual PWM Step-Down Converter in a 2mm x
2mm Package for WCDMA PA and RF Power
10 ______________________________________________________________________________________
Pin Description
PIN
NAME
FUNCTION
A1
REFBP
Reference Noise Bypass. Bypass REFBP to AGND with a 0.033礔 ceramic capacitor to reduce noise
on the LDO output. REFBP is internally pulled down through a 1k& resistor during shutdown.
A2
AGND
Low-Noise Analog Ground. Connect AGND to the ground plane at a single point away from high
switching currents. See the PCB Layout section.
A3
REFIN
DAC-Controlled Input. The output of the PA step-down converter is regulated to 2.5 x V
REFIN
. When
V
REFIN
 reaches 0.396 x V
CC
, bypass mode is enabled.
A4
PGND1
Power Ground for OUT1. Connect PGND1 to the ground plane near the input and output capacitor
grounds. See the PCB Layout section.
B1
LDO
200mA LDO Regulator Output. Bypass LDO with a 1礔 ceramic capacitor as close as possible to
LDO and ground. Leave LDO unconnected if not used.
B2
PAEN
OUT1 Enable Input. Connect PAEN to IN1 or logic-high for normal operation. Connect to ground or
logic-low to shut down OUT1. Internally connected to ground through an 800k& resistor.
B3
RFEN2
OUT2 and LDO Enable Input. Connect RFEN1 or RFEN2 to IN2 or logic-high for normal operation.
Connect RFEN1 and RFEN2 to ground or logic-low to shut down OUT2 and the LDO. Internally
connected to ground through an 800k& resistor.
B4
LX1   Inductor Connection. Connect an inductor from LX1 to the output of OUT1.
C1
OUT2
Output of OUT2. OUT2 is also the supply voltage input for the LDO. Bypass OUT2 with a 2.2礔
ceramic capacitor as close as possible to OUT2 and PGND2.
C2
RFEN1
OUT2 and LDO Enable Input. Connect RFEN1 or RFEN2 to IN2 or logic-high for normal operation.
Connect RFEN1 and RFEN2 to ground or logic-low to shut down OUT2 and the LDO. Internally
connected to ground through an 800k& resistor.
C3
V
CC
Supply Voltage Input for Internal Reference and Control Circuitry. Connect V
CC
 to a battery or supply
voltage from 2.7V to 5.5V. Bypass V
CC
 with a 0.1礔 ceramic capacitor as close as possible to V
CC
and AGND. Connect V
CC
, IN1, and IN2 to the same source.
C4
IN1
Supply Voltage Input for OUT1. Connect IN1 to a battery or supply voltage from 2.7V to 5.5V. Bypass
IN1 with a 4.7礔 ceramic capacitor as close as possible to IN1 and PGND1. Connect IN1, V
CC,
 and
IN2 to the same source.
D1
PGND2
Power Ground for OUT2. Connect PGND2 to the ground plane near the input and output capacitor
grounds. See the PCB Layout section.
D2
LX2   Inductor Connection. Connect an inductor from LX2 to the output of OUT2.
D3
IN2
Supply Voltage Input for OUT2. Connect IN2 to a battery or supply voltage from 2.7V to 5.5V. Bypass
IN2 with a 2.2礔 ceramic capacitor as close as possible to IN2 and PGND2. Connect IN2, V
CC
,
 
and
IN1 to the same source.
D4
PAOUT
PA Connection for Bypass Mode. Internally connected to IN1 using the internal bypass MOSFET
during bypass mode. PAOUT is internally connected to the feedback network for OUT1. Bypass
PAOUT with a 4.7礔 ceramic capacitor as close as possible to PAOUT and PGND1.
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