參數(shù)資料
型號: MAX8729
廠商: Maxim Integrated Products, Inc.
英文描述: Constant-Frequency, Half-Bridge CCFL Inverter Controller
中文描述: 固定頻率、半橋CCFL逆變控制器
文件頁數(shù): 10/26頁
文件大?。?/td> 395K
代理商: MAX8729
M
Constant-Frequency, Half-Bridge CCFL
Inverter Controller
10
______________________________________________________________________________________
Pin Description
PIN
NAME
FUNCTION
1
PCOMP
Compensation Node of the Phase-Lock Loop. Connect a 0.1μF capacitor between PCOMP and GND
to compensate the phase-lock loop.
Brightness-Control Select Input. Brightness can be adjusted with an analog voltage or with an
external sync signal. Connecting SEL to GND enables analog control at the CNTL pin. Connecting
SEL to V
CC
enables brightness control using an external sync signal at the LSYNC pin.
2
SEL
3
IN
Supply Input. Input to the internal 5.35V linear regulator that powers the device. Bypass IN to GND
with a 0.1μF ceramic capacitor.
4
V
CC
5.35V/10mA Linear-Regulator Output. V
CC
powers most of the control circuitry in the MAX8729.
Bypass V
CC
to GND with a 1μF ceramic capacitor.
System Ground
Fault-Timer Set Pin. Connect a 0.22μF capacitor from TFLT to GND to set the open-lamp fault delay
period to approximately 1.2s and the secondary short-circuit fault-delay period to approximately
10ms. See the
Setting the Fault-Delay Time
section for details.
5
GND
6
TFLT
7
CNTL
Brightness Control Input. The usable brightness control range is from 0 to 2V. V
CNTL
= 0 represents
the minimum brightness (10% DPWM duty cycle); 2V
V
CNTL
< 4.2V represents the full brightness
(100% DPWM duty cycle). The MAX8729 enters into slave mode when CNTL is connected to V
CC
.
See the
Digital PWM Dimming Control
section for details.
Shutdown Control Input. The MAX8729 shuts down when
SHDN
is pulled to GND.
DPWM Frequency Adjustment Pin. Connect a resistor from LF to GND to set the DPWM oscillator
frequency. LF is a logic input when CNTL is connected to V
CC
.
DPWM Oscillator Clock Output. LFCK is a logic input when CNTL is connected to V
CC
.
DPWM Signal Output. The DPWM output is used to control the DPWM frequency of the slave IC in
master-slave operation. See the
Slave Operation
section for details.
Phase-Shift Clock Output. PSCK is a logic input when CNTL is connected to V
CC
.
Main Switching Oscillator Clock Output. HFCK is a logic input when CNTL is connected to V
CC
.
Main Switching-Frequency Sync Input. Switching frequency can be synchronized with an external
signal on HSYNC. HSYNC has a Schmitt trigger input.
Switching-Frequency Adjustment Pin. Connect a resistor from HF to GND to set the main oscillator
frequency. HF is a logic input when CNTL is connected to V
CC
.
Phase-Shift Select Input. The PS1 and PS2 logic inputs select between four programmable phase
shifts (60°, 90°, 120°, and 180°) in master-slave operation. PS1 and PS2 should be in identical states
in each slave. See the
Phase Shift
section for details.
8
SHDN
9
LF
10
LFCK
11
DPWM
12
13
PSCK
HFCK
14
HSYNC
15
HF
16
PS2
17
COMP
Transconductance Error-Amplifier Output. A 0.01μF capacitor connected between COMP and GND
sets the rise and fall time of the lamp-current envelope during DPWM operation. See the
COMP
Capacitor Selection
section for details.
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