參數(shù)資料
型號: MAX8554
廠商: Maxim Integrated Products, Inc.
英文描述: 4.5V to 28V Input. Synchronous PWM Buck Controllers for DDR Termination and Point-of-Load Applications
中文描述: 4.5V至28V輸入、同步PWM buck控制器,適合DDR端接和負(fù)載點應(yīng)用
文件頁數(shù): 22/24頁
文件大?。?/td> 483K
代理商: MAX8554
Use R
DS(ON)
at T
J(MAX)
:
where I
GATE
is the average DH driver output current
determined by:
where R
DH
is the high-side MOSFET driver
s on-resis-
tance (1.4
typ) and R
GATE
is the internal gate resis-
tance of the MOSFET (~2
):
where V
GS
= V
VL
= 5V.
When the MAX8553 is sinking current, the high-side
MOSFET operates as a zero-voltage switch and the
low-side MOSFETs operate as a nonzero-voltage
switch.
In addition to the losses above, allow about 20% more
for additional losses due to MOSFET output capaci-
tances and low-side MOSFET body-diode reverse
recovery charge dissipated in the high-side MOSFET
that is not well defined in the MOSFET data sheet. Refer
to the MOSFET data sheet for thermal-resistance speci-
fications to calculate the PC board area needed to
maintain the desired maximum operating junction tem-
perature with the above calculated power dissipations.
To reduce EMI caused by switching noise, add a 0.1μF
ceramic capacitor from the high-side switch drain to
the low-side switch source, or add resistors in series
with DH and DL to slow down the switching transitions.
Adding series resistors increases the power dissipation
of the MOSFET, so ensure that this does not overheat
the MOSFET.
Control IC Power Dissipation
Power dissipation in the MAX8553/MAX8554 IC is pri-
marily due to the on-chip MOSFETs
gate drivers (DH
and DL). This power dissipation depends on the gate
charge of the external MOSFETs used. Power dissipa-
tion in the MAX8553 also depends on the VTTR load
current (I
VTTR
). Use the following equation to calculate
the power dissipation:
where Q
GH
and Q
GL
are the total gate charge of the
high-side and low-side MOSFETs, respectively. Select
the switching frequency and V
V+
correctly to ensure
the power dissipation does not exceed the package
power-dissipation requirement.
Applications Information
PC Board Layout
A properly designed PC board layout is important in
any switching regulator. The switching power stage
requires particular attention. If possible, mount all the
power components on the top-side of the board with
their ground terminals flush against one another. Follow
these guidelines for good PC board layout:
1) Keep the high-current paths short, especially at the
ground terminals. This practice is essential for sta-
ble, low-jitter operation.
2) Connect GND and PGND together at a single point.
3) Keep the power traces and load connections short.
This practice is essential for high efficiency. The use
of thick copper PC boards (2oz vs. 1oz) can notice-
ably enhance full-load efficiency. Correctly routing
PC board traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single m
of excess trace resistance caus-
es a measurable efficiency penalty.
4) LX and PGND connections to the low-side MOSFET
for current limiting must be made using Kelvin-
sense connections in order to guarantee the cur-
rent-limit accuracy. With 8-pin SO MOSFETs, this
can be done by routing power to the MOSFETs from
P
V
f
Q
(
Q
I
D
V
S
GH
GL
VTTR
=
(
)
×
×
+
)
+
[
]
+
P
Q
V
f
R
R
R
HSDR
G
GS
S
GATE
GATE
DH
=
×
×
×
+
I
V
R
R
GATE
DH
GATE
=
+
2 5
P
V
I
f
Q
Q
I
HSSW
IN
LOAD
S
GS
GD
GATE
=
×
×
×
+
P
V
V
I
R
HSCC
OUT
IN
LOAD
DS ON
(
=
×
(
)
×
)
2
M
4.5V to 28V Input, Synchronous PWM Buck Controllers
for DDR Termination and Point-of-Load Applications
22
______________________________________________________________________________________
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