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參數(shù)資料
| 型號： | MAX769 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Dual J-K Negative-Edge-Triggered Flip-Flops With Preset And Clear 16-CDIP -55 to 125 |
| 中文描述： | 2或3節(jié)電池、升/降壓型、雙向?qū)ず魴C(jī)系統(tǒng)電源IC |
| 文件頁數(shù)： | 9/16頁 |
| 文件大小： | 161K |
| 代理商： | MAX769 |
M
2 or 3-Cell, S tep-Up/Down,
Two-Way Pager S ystem IC
_______________________________________________________________________________________
9
_______________Detailed Desc ription
The MAX769 contains several functional blocks that
simplify the integration of power-supply and monitoring
functions within a 2 or 3-cell powered system. They are
described in the following subsections.
V oltage Regulators
Regulator outputs include the following:
OUT: Main switch-mode buck/boost output
REG1: 1.5
switch and output voltage clamp. Switches
REG1 to OUT and clamps REG1 at 3.3V when
OUT is set to 3.4V or more.
REG2: Linear-regulated, 24mA low-noise output that
regulates so that V
OUT
- V
REG2
is a set difference
voltage (10μA x R
OFS
). Output peak-to-peak ripple is
typically 2mV with a 10μF bypass capacitor at REG2.
REG2 clamps the output at 3.3V when OUT is set to
3.4V or more.
REG3: Low-noise, 1V linear regulator that supplies
2mA.
Main DC-DC Boost Converter (OUT)
OUT is the main DC-DC converter’s output. It supplies
current from the internal synchronous-rectified buck/
boost regulator and needs no external FETs or voltage-
setting resistors. The output voltage (V
OUT
) is adjusted
from 1.8V to 4.9V in 100mV steps (Tables 1 and 5) by
internal DAC control using a serial-data command.
OUT can supply up to 80mA, less the current supplied
to the other regulators (REG1, REG2, and REG3).
OUT can also be put into a low-current, pulse-skipping
Coast Mode (13μA typical quiescent current) by reset-
ting the RUN/COAST serial input bit. OUT supplies up
to 40mA in Coast Mode. Typically, when changing from
Run to Coast Mode, a lower OUT voltage is also set
(Table 4) to further reduce system operating current.
The extent of this reduction depends on the minimum
operating voltage of the system components when they
are in standby or sleep states.
OUT can be set as low as 1.8V; however, some Run
Mode functions are limited when V
OUT
is below 2.5V:
The allowed serial-interface clock rate is reduced.
Internal LX FET and DR1 and DR2 on-resistance
increases.
Logic Supply (REG1)
REG1 is not a regulator in the conventional sense, but
rather a 1.5
PFET that acts as either a switch or a volt-
age clamp, depending on the programmed OUT volt-
age. When OUT is set to 3.3V or less, REG1 operates
as a switch. When OUT is set to 3.4V or more, the
REG1 output clamps at 3.3V. This arrangement limits
V
REG1
to an acceptable voltage for logic when OUT is
programmed to a higher voltage (typically >4V) for
charging (see Charger Circuit and Backup Linear
Regulatorsections).
Low-Noise Analog Supply (REG2)
REG2 is a linear, 24mA low-dropout regulating circuit
whose input is R2IN. The REG2 output (V
REG2
) is set
by R
OFS
. R
OFS
does not set an absolute voltage, but
rather an offset level from R2IN (Figure 2). V
REG2
is set
by:
V
REG2
= V
R2IN
- 10μA x R
OFS
Typically R2IN and R
OFS
are tied to OUT, in which
case:
V
OUT
- V
REG2
= 10μA x R
OFS
ROFS adjusts V
REG1
- V
REG2
to allow REG2 noise
rejection to be traded for voltage drop and consequent
efficiency loss. A 15k
(typical) R
OFS
value sets a
150mV voltage difference. R2IN is typically supplied
from OUT or REG1, but can be connected elsewhere
as long as the voltage applied to R2IN does not exceed
V
OUT
. For lowest output noise on REG2, connect R2IN
to REG1.
Note that the REG2 output also clamps at 3.3V when
OUT is set to 3.4V or higher.
Low-Noise, 1V Analog Supply (REG3)
REG3 is a 1V, low-noise linear regulator that supplies
up to 2mA. REG3’s input is internally connected to
REG2.
PWM Frequenc y S ync hronization
The DC-DC converter switching frequency in pulse-
width-modulation (PWM) mode is nominally 270kHz if
no synchronization clock is supplied and FILT is tied to
REF. If the PLL is used, a filter network is connected to
FILT, a clock is applied to SYNC, and the internal oscil-
lator locks to seven times the input clock rate. The
MAX769 is designed for a 38.4kHz SYNC input and
hence a 268.8kHz operating frequency. PWM switching
frequency is unaffected by the serial-data clock rate.
V oltage Detec tors (LBO and Reset)
The MAX769 contains two voltage-detector inputs: LBI
and RSIN. The LBI and RSIN comparator outputs are
open-drain pins (LBO and RSO) for a real-time hard-
ware output. LBO is also readable via the serial inter-
face. Both LBI and RSIN trigger at a 0.6V input
threshold and have about 18mV hysteresis. RSO also
triggers the MAX769 internal power-on reset (POR).
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