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參數(shù)資料
| 型號(hào)： | MAX769 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Dual J-K Negative-Edge-Triggered Flip-Flops With Preset And Clear 16-CDIP -55 to 125 |
| 中文描述： | 2或3節(jié)電池、升/降壓型、雙向?qū)ず魴C(jī)系統(tǒng)電源IC |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 161K |
| 代理商： | MAX769 |
M
2 or 3-Cell, S tep-Up/Down,
Two-Way Pager S ystem IC
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(OUT = 3.0V, BATT = 3.6V, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
CONDITIONS
PARAMETER
SERIAL-INTERFACE TIMING SPECIFICATIONS
(Note 9)
%
-3.5
3.5
OUT Error, Coast Mode
(Note 11)
%
mV
Coast Mode, OUT = 1.8V to 4.9V
-3.5
30
3.5
170
OUT Error, Run Mode (Note 12)
OUT DAC Step Size (Note 13)
Circuit of Figure 2, OUT = 3.0V, BATT = 3.0V
Run Mode, OUT = 1.8V to 4.9V
Coast or Run Mode, OUT = 1.8V to 4.9V
Circuit of Figure 2, OUT = 3.0V, BATT = 3.0V
BATT = 1.6V to 4.5V
OUT = 3.0V
mV
%
25
83
OUT Line Regulation
Maximum LX Duty Cycle
I
OUT
= 80mA, C
OUT
= 47μF with ESR < 0.25
During the inductor charge cycle
mVp-p
mA
70
350
OUT Voltage Ripple
LX Switch Current Limit
LX1, LX2, BATT = 3.0V
0.9
1.3
1.8
2.6
LX On-Resistance (Note 14)
ns
ns
ns
50
50
100
CS
to SCL Hold Time (t
CSH
)
CS
Pulse Width High (t
CSW
)
SCL Pulse Width High or Low
(t
CH
, t
CL
)
DC-DC CONVERTER
CS
to SCL Setup Time (t
CSS
)
ns
ns
100
50
SDI Setup Time (t
DS
)
SDI Hold Time (t
DH
)
NMOS
PMOS
T
A
= +25°C, FILT connected to REF
f
SYNC
= 38.4kHz
f
SYNC
= 38.4kHz, FILT Network = 1nF
(22nF + 10k
)
f
SYNC
= 38.4kHz, FILT Network = 1nF
(22nF + 10k
)
kHz
kHz
kHz
ms
210
270
268.8
±15
1
325
Frequency, Free-Run
Frequency, Locked
J itter (Note 15)
Capture Time (Note 15)
NICD CHARGER
Backup Mode, NICD = 3.3V
ns
70
CS
to SDO Disable (t
TR
)
5
10
25
Backup-Regulator
On-Resistance (Note 16)
ns
50
0.2V < (OUT - NICD) < 2V, 15mA_CHG = 1
0.2V < (OUT - NICD) < 2V, 1mA_CHG = 1
OUT = 2.8V, I
OUT
= 20mA, NICD = 3.3V
mA
mA
%
mA
80
115
7
25
1.5
3.5
Output Current, Run Mode
(Note 10)
mA
15
40
Current High
Current Low
OUT Error, Backup Regulator
Output Current, Coast Mode
(Note 10)
UNITS
MIN
TYP
MAX
0.45
-3.5
50% duty cycle
MHz
5
SCL Maximum Clock Rate
76
300
400
ns
ns
70
70
CS
to SDO Output Valid (t
DV
)
SCL to SDO Output Valid (t
DO
)
I
OUT
= 1mA to 80mA, Run Mode
mV
25
OUT Load Regulation
100
PHASE-LOCKED LOOP (PLL)
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