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參數(shù)資料
| 型號： | MAX7652ECB |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Flash Programmable 12-Bit Integrated Data-Acquisition Systems |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, MO-136BJ, TQFP-64 |
| 文件頁數(shù)： | 21/36頁 |
| 文件大小： | 479K |
| 代理商： | MAX7652ECB |
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Since the acquisition time is limited to eight clock peri-
ods, the acquired voltage at C
HOLD
can have signifi-
cant error if the analog input source impedance (R
s
) is
large. Limit the worst-case error to 1/2 LSB by ensuring,
Rs < 0.9 t
CLK
/ C
HOLD
where t
CLK
is the clock period. Smaller R
s
values may
be necessary if an antialiasing filter is used.
The ADC continuously samples the positive and negative
difference between the two external reference voltages
REF+ and REF- by reconfiguring capacitor C
REF
over
alternate eight clock-period intervals. Switch pairs 1 and
2 are forced off and on, respectively, on the rising edge
of clock cycle five to ensure synchronization with conver-
sions. Capacitor C
HOLD
also charges to the difference
between REF+ and REF- on the rising edge of clock
cycle 29 and remains charged until the next conversion.
Nevertheless, continuous C
REF
charging requirements
dominate loading at the REF+ and REF- inputs.
Analog Inputs
The MAX7651/MAX7652 operate in either single-ended
or differential mode. In single-ended mode, one of eight
input channels (AIN0
–
AIN7) is assigned to AIN+, and
ACOM is assigned to AIN- (see Figure 6). In differential
mode, the eight input channels are assigned to AIN+
and AIN- with four distinct pairings. Table 6 shows the
input assignments for different values of bits M3, M2,
M1, and M0 in the A/D Control SFR (see
ADC Special
Function Registers
).
Analog Input Protection
Internal protection diodes clamp the analog inputs to
AV
DD
and AGND, so channels can swing within AGND -
M
Flash Programmable 12-Bit Integrated
Data-Acquisition Systems
______________________________________________________________________________________
21
SFR
WRITE
CLK
2
3
1
4
5
INPUT SAMPLE
1
1
3
4
5
2
2
2.1pF
V
REF+
V
REF+
V
REF-
AIN-
3
4
AIN+
1.50pF
C
HOLD
V
REF-
C
REF
Figure 6. ADC Input Structure and Switch Timing
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| MAX765C/D | 功能描述:直流/直流開關調(diào)節(jié)器 -12V or Adjustable High-Efficiency Low IQ DC-DC Inverters RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開關頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數(shù)量: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
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| MAX765CPA+ | 功能描述:直流/直流開關調(diào)節(jié)器 5/12/15/AdjV DC/DC Inverter RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開關頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數(shù)量: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
| MAX765CSA | 功能描述:直流/直流開關調(diào)節(jié)器 5/12/15/AdjV DC/DC Inverter RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開關頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數(shù)量: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
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