參數(shù)資料
型號： MAX7652ECB
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 模擬信號調理
英文描述： Flash Programmable 12-Bit Integrated Data-Acquisition Systems
中文描述： SPECIALTY ANALOG CIRCUIT, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, MO-136BJ, TQFP-64
文件頁數(shù)： 15/36頁
文件大?。?/td> 479K
代理商： MAX7652ECB
M
Flash Programmable 12-Bit Integrated
Data-Acquisition Systems
______________________________________________________________________________________
15
Pin Description (continued)
PIN
NAME
FUNCTION
P3.1: Bit 1 for General Purpose I/O Port 3
TXD0: Transmit Serial Output for Serial Port
P3.0: Bit 0 for General Purpose I/O Port 3 (least significant bit)
RXD0: Receive Serial Input for Serial Port
Digital Ground. Connect DGND to AGND at the power source. Connect pins 27, 39, and 61 together.
Positive Digital Supply Voltage. Bypass with a 0.1μF in parallel with a 10μF low ESR capacitor to DGND.
Connect pins 28, 40, and 62 together.
P2.0: Bit 0 for General Purpose I/O Port 2 (least significant bit)
A8: Bit 8 for Internal Flash Memory Address
P2.1: Bit 1 for General Purpose I/O Port 2
A9: Bit 9 for Internal Flash Memory Address
P2.2: Bit 2 for General Purpose I/O Port 2
A10: Bit 10 for Internal Flash Memory Address
P2.3: Bit 3 for General Purpose I/O Port 2
A11: Bit 11 for Internal Flash Memory Address
P2.4: Bit 4 for General Purpose I/O Port 2
A12: Bit 12 for Internal Flash Memory Address
P2.5: Bit 5 for General Purpose I/O Port 2
Upper and Lower Internal Flash Memory Select (see Table 2)
P2.6: Bit 6 for General Purpose I/O Port 2
Flash Programming Mode Select (see Table 2)
P2.7: Bit 7 for General Purpose I/O Port 2 (most significant bit)
Flash Programming Mode Select (see Table 2)
25
P3.1/
TXD0
26
P3.0/
RXD0
27
DGND
28
DV
DD
29
P2.0/A8
30
P2.1/A9
31
P2.2/A10
32
P2.3/A11
33
P2.4/A12
34
P2.5
35
P2.6
36
P2.7
37
PSEN
Program Store Enable (active-low). Qualifies program read from external devices. To ensure flash data
integrity during RST insertions, R
LOAD
must be greater than or equal to 200k
.
ALE: Address Latch Enable. To ensure flash data integrity during RST insertions, R
LOAD
must be greater
than or equal to 200k
.
PROG
: Flash Memory Program Pulse
Digital Ground. Connect pins 27, 39, and 61 together.
Positive Digital Supply Voltage. Bypass with a 0.1μF in parallel with a 10μF low ESR capacitor to DGND.
Connect pins 28, 40 and 62 together.
P0.0: Bit 0 for General Purpose I/O Port 0 (least significant bit)
AD0: Bit 0 for Internal Flash Memory Data or External Memory I/O Data (least significant bit)
P0.1: Bit 1 for General Purpose I/O Port 0
AD1: Bit 1 for Internal Flash Memory Data or External Memory I/O Data
P0.2: Bit 2 for General Purpose I/O Port 0
AD2: Bit 2 for Internal Flash Memory Data or External Memory I/O Data
P0.3: Bit 3 for General Purpose I/O Port 0
AD3: Bit 3 for Internal Flash Memory Data or External Memory I/O Data
P0.4: Bit 4 for General Purpose I/O Port 0
AD4: Bit 4 for Internal Flash Memory Data or External Memory I/O Data
38
ALE/
PROG
39
DGND
40
DV
DD
41
P0.0/AD0
42
P0.1/AD1
43
P0.2/AD2
44
P0.3/AD3
45
P0.4/AD4
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