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參數(shù)資料
| 型號： | MAX7652CCB |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Flash Programmable 12-Bit Integrated Data-Acquisition Systems |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, MO-136BJ, TQFP-64 |
| 文件頁數(shù)： | 24/36頁 |
| 文件大?。?/td> | 479K |
| 代理商： | MAX7652CCB |
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M
Flash Programmable 12-Bit Integrated
Data-Acquisition Systems
24
______________________________________________________________________________________
(Output B), the corresponding output transitions from
low to high (Figure 9).
Writing 00H to PWDA or PWDB, yields a waveform with
100% duty cycle (High), and writing FFH to PWDA or
PWDB yields a waveform with 0% duty cycle (Low).
Writing an intermediate register value y, yields a wave-
form with duty cycle (1 - y / 255)
100%. Tables 10, 11,
and 12 show the formats of the PWPS, PWDA, and
PWDB SFR
’
s.
External low-pass filters are needed to obtain DC volt-
ages between 0 and DV
DD
from the PWM outputs.
Simple RC filters are preferred. Choose R >2k
to
avoid excessive loading, and choose C <0.1μF to avoid
large transient currents that reflect the PWM switching
action. Each filtered PWM output can source or sink up
to 2mA. Do not exceed this specification. If larger out-
put capability is required, provide an appropriate buffer
such as a unity-gain op amp. PWM circuitry and PWM
Outputs A and B are enabled with the Pulse-Width
Modulator Control (PWMC) SFR. Table 13 shows the
PWMC SFR format.
Watchdog Timer
The MAX7651/MAX7652 features a watchdog timer that
resolves irregular software control. The watchdog timer
resets the microprocessor if software fails to reset the
timer within one of four pre-selected time intervals. The
timer generates an optional interrupt after 2
16
, 2
19
, 2
22
,
or 2
25
clock periods of the external oscillator. It gener-
ates the reset signal after an additional 512 clock peri-
ods. Table 14 indicates specific interrupt and reset
times that apply for a 12MHz clock frequency.
Five watchdog-related control bits and two status flags
are located in different special function registers. Table
15 shows the particular functions and SFR locations.
8051-Compatible Peripherals
Parallel I/O Ports
Like other 8051-based systems, the MAX7651/
MAX7652 features four 8-bit parallel ports that support
general input and output, address and data lines, and
various special functions. Each bidirectional port has a
latch register (SFRs P0, P1, P2, and P3), an input
buffer, and an output driver.
Port P0 is open-drain. Writing a logic level 1 to a P0 pin
establishes a high-impedance input. When used as a
general-purpose output, a P0 pin requires an external
pull-up resistor to validate a logic level 1. When used
as an address/data output, a P0 pin features an internal
active high driver. Port 0 is a bidirectional Flash data
I/O port during Flash programming and verification.
Port 1: Port 1 is a bidirectional I/O port with internal
pullups. Port 1 pins that have 1
’
s written to them are
pulled high by the internal pullups and can serve as
inputs. Port 1 receives low-order address bytes during
Flash programming and verification.
Port 2: Port 2 is a bidirectional I/O port with internal
pullups. Port 2 pins that have 1
’
s written to them are pulled
high by the internal pullups and can serve as inputs. Port
2 also serves as the high-order address and data bus (for
16-bit operations) during accesses to external memory,
using strong internal pullups when emitting 1
’
s.
Port 3: Port 3 is a bidirectional I/O port with internal
pullups. Port 3 pins that have 1
’
s written to them are
pulled high by the internal pullups and can serve as
inputs.
The P1 and P3 ports support the special functions list-
ed in Table 16. Write a
“
1
”
to the corresponding bit in
the port register to enable the alternative function.
USER ACCESSIBLE SFR REGISTER
USER
ACCESSIBLE
SFR REGISTER
USER ACCESSIBLE SFR REGISTER
SFR PWDA
REGISTER
MODULO 255
COUNTER
PWMA
OUTPUT
PWMB
OUTPUT
PWPS
FROM
CRYSTAL
OSCILLATOR
SFR PWDB
REGISTER
MAGNITUDE
COMPARATOR >=
MAGNITUDE
COMPARATOR >=
DIVIDE
BY TWO
Figure 8. PWM Block Diagram
TPW
HIGH
TPW
PERIOD
TPW
PERIOD
= 2(PWPS+1) 255/F
OSC
TPW
HIGH
= (255 - PWD(X))/255
×
TPW
PERIOD
F
OSC
Figure 9. PWM Output Waveform
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX7652ECB | Flash Programmable 12-Bit Integrated Data-Acquisition Systems |
| MAX766ESA | -5V/-12V/-15V or Adjustable, High-Efficiency, Low IQ DC-DC Inverters |
| MAX765 | -5V/-12V/-15V or Adjustable, High-Efficiency, Low IQ DC-DC Inverters |
| MAX764-MAX766 | -5V/-12V/-15V or Adjustable, High-Efficiency, Low IQ DC-DC Inverters |
| MAX764MJA | ODS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX7652ECB | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| MAX765C/D | 功能描述:直流/直流開關(guān)調(diào)節(jié)器 -12V or Adjustable High-Efficiency Low IQ DC-DC Inverters RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開關(guān)頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數(shù)量: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
| MAX765C/D DIE | 制造商:Maxim Integrated Products 功能描述: |
| MAX765CPA | 功能描述:直流/直流開關(guān)調(diào)節(jié)器 5/12/15/AdjV DC/DC Inverter RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開關(guān)頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數(shù)量: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
| MAX765CPA+ | 功能描述:直流/直流開關(guān)調(diào)節(jié)器 5/12/15/AdjV DC/DC Inverter RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開關(guān)頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數(shù)量: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
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