參數(shù)資料
型號(hào)： MAX7359ETG+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 14/20頁(yè)
文件大?。?/td> 0K
描述： IC KEY SWITCH 2WIRE 24-TQFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
應(yīng)用： 移動(dòng)電話，PDA，播放器
接口： I²C
電源電壓： 1.65 V ~ 3.6 V
封裝/外殼： 24-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 24-TQFN-EP（3.5x3.5）
包裝： 帶卷 (TR)
安裝類型： 表面貼裝
MAX7359
2-Wire Interfaced Low-EMI
Key Switch Controller/GPO
_______________________________________________________________________________________
3
I2C TIMING CHARACTERISTICS
(VCC = +1.62V to +3.6V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +2.5V, TA = +25°C.) (Notes 2, 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Capacitance
(SCL, SDA, AD0)
CIN
(Notes 4, 5)
10
pF
SCL Serial-Clock Frequency
fSCL
Bus timeout disabled
0
400
kHz
Bus Free Time Between a STOP
and a START Condition
tBUF
1.3
s
Hold Time (Repeated) START
Condition
tHD, STA
0.6
s
Repeated START Condition
Setup Time
tSU, STA
0.6
s
STOP Condition Setup Time
tSU, STO
0.6
s
Data Hold Time
tHD, DAT
(Note 6)
0.9
s
Data Setup Time
tSU, DAT
100
ns
SCL Clock Low Period
tLOW
1.3
s
SCL Clock High Period
tHIGH
0.7
s
Rise Time of Both SDA and SCL
Signals, Receiving
tR
(Notes 4, 5)
20 +
0.1Cb
300
ns
Fall Time of Both SDA and SCL
Signals, Receiving
tF
(Notes 4, 5)
20 +
0.1Cb
300
ns
Fall Time of SDA Transmitting
tF, TX
(Notes 4, 7)
20 +
0.1Cb
250
ns
Pulse Width of Spike Suppressed
tSP
(Notes 4, 8)
50
ns
Capacitive Load for Each Bus Line
Cb
(Note 4)
400
pF
Note 2: All parameters are tested at TA = +25°C. Specifications over temperature are guaranteed by design.
Note 3: All digital inputs at VCC or GND.
Note 4: Guaranteed by design.
Note 5: Cb = total capacitance of one bus line in pF. tR and tF measured between +0.3VCC and +0.7VCC.
Note 6: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge
the undefined region of SCL’s falling edge.
Note 7: ISINK ≤ 6mA.
Note 8: Input filters on the SDA, SCL, and AD0 inputs suppress noise spikes less than 50ns.
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