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| 型號： | MAX7319 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | 4-Bit D-type Registers with 3-State Outputs 16-CFP -55 to 125 |
| 中文描述： | I²C端口擴展器，具有8路輸入，可屏蔽瞬態(tài)檢測 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 251K |
| 代理商： | MAX7319 |
M
I
2
C Port Expander with Eight Inputs and
Maskable Transition Detection
_______________________________________________________________________________________
3
PORT AND INTERRUPT
INT
TIMING CHARACTERISTICS
(V+ = +1.71V to +5.5V, T
A
= -40
°
C to +125
°
C, unless otherwise noted. Typical values are at V+ = +3.3V, T
A
= +25
°
C.) (Note 1)
PARAMETER
SYMBOL
t
PSU
t
PH
t
IV
t
IP
CONDITIONS
MIN
0
4
TYP
MAX
UNITS
μs
μs
μs
μs
Port Input Setup Time
Port Input Hold Time
INT
Input Data Valid Time
INT
Reset Delay Time from STOP
C
L
≤
100pF
C
L
≤
100pF
C
L
≤
100pF
C
L
≤
100pF
4
4
INT
Reset Delay Time from
Acknowledge
t
IR
C
L
≤
100pF
4
μs
TIMING CHARACTERISTICS
(V+ = +1.71V to +5.5V, T
A
= -40
°
C to +125
°
C, unless otherwise noted. Typical values are at V+ = +3.3V, T
A
= +25
°
C.) (Note 1)
PARAMETER
SYMBOL
f
SCL
CONDITIONS
MIN
TYP
MAX
400
UNITS
kHz
Serial Clock Frequency
Bus Free Time Between a STOP
and a START Condition
t
BUF
1.3
μs
Hold Time (Repeated) START
Condition
t
HD, STA
0.6
μs
Repeated START Condition
Setup Time
t
SU, STA
0.6
μs
STOP Condition Setup Time
Data Hold Time
Data Setup Time
SCL Clock Low Period
SCL Clock High Period
Rise Time of Both SDA and SCL
Signals, Receiving
t
SU, STO
t
HD, DAT
t
SU, DAT
t
LOW
t
HIGH
0.6
μs
μs
ns
μs
μs
(Note 2)
0.9
100
1.3
0.7
t
R
(Notes 3, 4)
20 +
0.1C
b
300
ns
Fall Time of Both SDA and SCL
Signals, Receiving
t
F
(Notes 3, 4)
20 +
0.1C
b
300
ns
Fall Time of SDA, Transmitting
t
F,TX
(Notes 3, 4)
20 +
0.1C
b
50
250
ns
Pulse Width of Spike Suppressed
t
SP
(Note 5)
ns
Capacitive Load for Each Bus
Line
C
b
(Note 3)
400
pF
RST
Pulse Width
t
W
500
ns
RST
Rising to START Condition
Setup Time
t
RST
1
μs
Note 1:
All parameters are tested at T
A
= +25
°
C. Specifications over temperature are guaranteed by design.
Note 2:
A master device must provide a hold time of at least 300ns for the SDA signal (referred to V
IL
of the SCL signal) to bridge
the undefined region of SCL
’
s falling edge.
Note 3:
Guaranteed by design.
Note 4:
C
b
= total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3 x V+ and 0.7 x V+, I
SINK
≤
6mA.
Note 5:
Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
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