參數(shù)資料
型號: MAX6877
廠商: Maxim Integrated Products, Inc.
英文描述: Dual-/Triple-Voltage, Power-Supply Trackers/Sequencers/Supervisors
中文描述: 雙/三電壓、電源跟蹤器/排序器/監(jiān)控器
文件頁數(shù): 20/24頁
文件大小: 307K
代理商: MAX6877
M
Dual-/Triple-Voltage, Power-Supply
Trackers/Sequencers/Supervisors
20
______________________________________________________________________________________
When a fault is detected, for a period of t
RETRY
, GATE_
remains off and the 100
pulldowns are turned on.
After the t
RETRY
period, the device waits t
DELAY
and
retries power-up if all power-up conditions are met (see
Figure 8). These include all V
SET_
> 0.5V, EN/
UV
>
V
EN_R
, OUT_ voltages < V
TH_PL
. The autoretry period,
t
RETRY
, is a function of C
SLEW
; see Table 1.
When the device is in latch mode and a fault occurs,
FAULT
asserts and all outputs are latched off. To
unlatch OUT_ after a fault disappears, cycle EN/
UV
or
cycle V
CC
and the inputs (IN_) below the 2.7V UVLO
threshold. After EN/
UV
goes high, the device waits a
t
RETRY
period then tries to power-up again. If V
CC
and
all IN_ are cycled below 2.7V, the device tries to power-
up immediately.
Power-Good Output (PG/
RST
)
The MAX6877/MAX6878 include a power-good (PG/
RST
)
output. PG/
RST
is an open-drain output and requires an
external pullup resistor.
All the OUT_ outputs must exceed their IN_ referenced
thresholds (IN_ x V
TH_PG
) for the selected reset timeout
period t
TIMEOUT
(see the
TIMEOUT Period Input
sec-
tion) before PG/
RST
asserts high. PG/
RST
stays low for
the selected reset timeout period (t
TIMEOUT
) after all
the OUT_ voltages exceed their IN_ referenced thresh-
olds. PG/
RST
goes low when V
SET_
< V
TH
or V
EN/
UV
<
V
EN_R
(see Figure 3).
Applications Information
MOSFET Selection
The external pass MOSFET is connected in series with
the sequenced power-supply source. Since the load
current and the MOSFET drain-to-source impedance
(R
DS
) determine the voltage drop, the on characteris-
tics of the MOSFET affect the load supply accuracy.
The MAX6877/MAX6878/MAX6879 fully enhance the
external MOSFET out of its linear range to ensure the
lowest drain-to-source on-impedance. For highest sup-
ply accuracy/lowest voltage drop, select a MOSFET
with an appropriate drain-to-source on-impedance with
a gate-to-source bias of 4.5V to 6.0V.
Layout and Bypassing
For better noise immunity, bypass each of the IN_
inputs to GND with 0.1μF capacitors installed as close
to the device as possible. Bypass ABP to GND with a
1μF capacitor installed as close to the device as possi-
ble. ABP is an internally generated voltage and must
not be used to supply power to external circuitry.
Selector Guide
PART
CHANNEL
TIMEOUT
SELECTABLE
PG/
RST
MARGIN
V
CC
MAX6877
MAX6878
MAX6879
3
2
2
Yes
Yes
No
Yes
Yes
No
Yes
Yes
No
Yes
Yes
No
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