參數(shù)資料
型號(hào): MAX6877
廠商: Maxim Integrated Products, Inc.
英文描述: Dual-/Triple-Voltage, Power-Supply Trackers/Sequencers/Supervisors
中文描述: 雙/三電壓、電源跟蹤器/排序器/監(jiān)控器
文件頁數(shù): 18/24頁
文件大?。?/td> 307K
代理商: MAX6877
M
Dual-/Triple-Voltage, Power-Supply
Trackers/Sequencers/Supervisors
18
______________________________________________________________________________________
voltages below the adjusted thresholds to avoid signal-
ing an error. The state of PG/
RST
and
FAULT
outputs
does not change while
MARGIN
is low. PG/
RST
,
FAULT
, and all monitoring functions are disabled while
MARGIN
is low.
MARGIN
makes it possible to vary the
supplies without a need to adjust the thresholds to pre-
vent tracker/sequencer alerts or faults. Drive
MARGIN
high or leave it unconnected for normal operating
mode.
Slew-Rate Control Input (SLEW)
The reference ramp voltage slew rate during any con-
trolled power-up/down phase can be programmed in
the 90V/s to 950V/s range by connecting a capacitor
(C
SLEW
) from SLEW to ground. Use the following for-
mula to calculate the typical slew rate:
Slew Rate = (9.35 x 10
-8
)/ C
SLEW
where slew rate is in V/s and C
SLEW
is in farads.
The capacitor at C
SLEW
also sets the
FAULT
timeout
period (t
FAULT
) and
FAULT
retry timeout period
(t
RETRY
) (see Table 1).
For example, if C
SLEW
= 100pF, we have t
RETRY
=
350ms, t
FAULT
= 21.91ms, slew rate = 935V/s. For
example, if C
SLEW
= 1nF, we have t
RETRY
= 3.5s,
t
FAULT
= 219ms, slew rate = 93.5V/s.
C
SLEW
is the capacitor on the SLEW pad, and must be
large enough to make the parasitic capacitance negli-
gible. C
SLEW
should be in the range of 100pF <
C
SLEW
< 1nF.
Table 1. C
SLEW
Timing Formulas
Limiting Inrush Current
The capacitor connected at SLEW controls the OUT_S
slew rate, thus controlling the inrush current required to
charge the load capacitor at the outputs (OUT_). Using
the programmed slew rate, limit the inrush current by
using the following formula:
I
INRUSH
= C
OUT
x SR
where I
INRUSH
is in amperes, C
OUT
is in farads, and SR
is in V/s.
Delay Time Input (DELAY)
To adjust the desired delay period (t
DELAY
) before
tracking/sequencing is enabled, connect a capacitor
(C
DELAY
) between DELAY to ground (see Figures 1 to 8).
The selected delay time is also enforced when EN/
UV
rises from low to high when all the input voltages
(IN1/IN2/IN3) are present. Use the following formula to
calculate the delay time:
t
DELAY
= 200μs + (500k
x C
DELAY
)
where t
DELAY
is in μs and C
DELAY
is in farads. Leave
DELAY unconnected for the default 200μs delay.
Timeout Period Input (TIMEOUT)
These devices feature a PG/
RST
timeout period.
Connect a capacitor (C
TIMEOUT
) from TIMEOUT to
ground to program the PG/
RST
timeout period. After all
OUT_ outputs exceed their IN_ referenced thresholds
(V
TH_PG
), PG/
RST
remains low for the selected timeout
period, t
TIMEOUT
(see Figure 3):
t
TIMEOUT
= 200μs + (500k
x C
TIMEOUT
)
where t
TIMEOUT
is in μs and C
TIMEOUT
is in farads.
Leave TIMEOUT unconnected for the default 200μs
timeout delay.
Logic-Enable Input (EN/
UV
)
Drive logic EN/
UV
input above V
EN_R
to initiate voltage
tracking/sequencing during the power-up operation.
Drive logic EN/
UV
below V
EN_F
to initiate tracking
power-down operation. Connect EN/
UV
to an external
resistor-divider network to set the external undervoltage
lockout threshold.
OUT1/OUT2/OUT3
The MAX6877 monitors three and MAX6878/MAX6879
monitor two OUT_ outputs to control the tracking/
sequencing performance. After the internal supply
(ABP) exceeds the minimum voltage (2.7V) require-
ments, EN/
UV
> V
EN_R
, and IN1/IN2/IN3 are all greater
than their adjusted SET_ thresholds, OUT1/OUT2/OUT3
begin to track or sequence.
TIME PERIOD
Slew Rate
t
RETRY
t
FAULT
FORMULAS
(9.35 x 10
-8
) / C
SLEW
3.506 x 10
9
x C
SLEW
2.191 x 10
8
x C
SLEW
IN_
R1
R2
V
IN_
SET_
MAX6877
MAX6878
MAX6879
Figure 9. Setting the Undervoltage (UVLO) Thresholds
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