參數(shù)資料
型號: MAX6876ETX+T
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 電源管理
英文描述: EEPROM-Programmable, Quad, Power-Supply Tracker/Sequencer Circuit
中文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, QCC36
封裝: 6 X 6 MM, 0.80 MM HEIGHT, MO-220WJJD-1, TQFN-36
文件頁數(shù): 3/39頁
文件大?。?/td> 425K
代理商: MAX6876ETX+T
MAX6876
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
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11
Pin Description (continued)
PIN
NAME
FUNCTION
7
OC
Active-Low, Open-Drain Overcurrent Output. OC asserts low if any monitored IN_ to OUT_ voltage
falls out of the selected percentage of the IN_ voltage range (VTH_OC) for more than the programmed
tOC. OC monitoring begins only after supply tracking or sequencing has been completed and is
disabled during power-down operation.
8
REM
Open-Drain Bus Removal Output. REM signals when it is safe to remove the card after a controlled
track/sequence-down operation. REM goes high impedance when all VOUT_ < VTH_PL. REM requires
an external pullup resistor. In master/slave mode, REM can be ORed together (the common REM
connection remains low if any VOUT_ > VTH_PL threshold) (see the Typical Application Circuit and the
Bus Removal Output (REM) section).
9
FAULT
Active-Low, Open-Drain Tracking Fault Alert Output or Input. FAULT asserts low if a tracking failure is
present for longer than the specified fault period or if tracking voltages fails by more than ±250mV
(see the FAULT section).
10
RESET
Active-Low, Open-Drain Reset or Power-Good Output. RESET is low during power-up and power-
down tracking. RESET goes high after all selected OUT_ outputs exceed their selected thresholds
and the reset timeout period tRESET has expired. The reset timeout period is internally selectable.
RESET requires an external pullup resistor.
11
ENABLE
Logic ENABLE Input. ENABLE must be high to enable voltage tracking/sequencing power-up
operation. OUT_ begins tracking down when ENABLE is low. Connect to ABP if not used.
12
MARGIN
Active-Low Margin Input. The MARGIN function allows systems to be tested with supply voltages
outside their normal ranges without affecting supply tracking/sequencing or reset states. MARGIN
functionality is usually enabled after systems have powered up in normal mode. The MARGIN
functionality is disabled (returns to normal monitoring mode) after MARGIN returns high. MARGIN is
internally pulled up to ABP through a 100k
resistor.
13, 23
N.C.
No Connection. Not internally connected.
14
MR
Active-Low Manual Reset Input. When MR is low, RESET goes low and remains asserted for the
selected timeout period after MR is pulled high. MR is internally pulled up to ABP through a 100k
resistor.
15
SDA
Serial-Interface Data Input/Output (Open-Drain). SDA requires an external pullup resistor.
16
SCL
Serial-Interface Clock Input. SCL requires an external pullup resistor.
17
A0
18
A1
Serial-Interface Address Inputs. The inputs allow up to four MAX6876 devices to be addressed when
sharing a common data bus. A1 and A0 should be connected to GND or ABP.
19
PG1
20
PG2
21
PG3
22
PG4
Power-Good Output, Open-Drain. Each PG_ output signals when its monitored OUT_ voltage is within
the selected percentage of the IN_ voltage range (VTH_PG). PG_ is low until OUT_ exceeds the
programmable threshold (VTH_PG) for more than tPOK. PG_ outputs are open-drain and require
external pullups if used.
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MAX6877ETG+ 功能描述:監(jiān)控電路 Triple Power-Sup Sequencer RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲(典型值):10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel
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