參數(shù)資料
型號: MAX6876ETX+T
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 電源管理
英文描述: EEPROM-Programmable, Quad, Power-Supply Tracker/Sequencer Circuit
中文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, QCC36
封裝: 6 X 6 MM, 0.80 MM HEIGHT, MO-220WJJD-1, TQFN-36
文件頁數(shù): 20/39頁
文件大?。?/td> 425K
代理商: MAX6876ETX+T
MAX6876
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
______________________________________________________________________________________
27
Repeated START Conditions
A REPEATED START (SR) condition may indicate a
change of data direction on the bus. Such a change
occurs when a command word is required to initiate a
read operation (see Figure 12). SR may also be used
when the bus master is writing to several I2C devices
and does not want to relinquish control of the bus. The
MAX6876 serial interface supports continuous write
operations with or without an SR condition separating
them. Continuous read operations require SR condi-
tions because of the change in direction of data flow.
Acknowledge
The acknowledge bit (ACK) is the 9th bit attached to
any 8-bit data word. The receiving device always gen-
erates an ACK. The MAX6876 generates an ACK when
receiving an address or data by pulling SDA low during
the 9th clock period (Figure 13). When transmitting
data, such as when the master device reads data back
from the MAX6876, the device waits for the master
device to generate an ACK. Monitoring ACK allows for
detection of unsuccessful data transfers. An unsuc-
cessful data transfer occurs if the receiving device is
busy or if a system fault has occurred. In the event of
an unsuccessful data transfer, the bus master should
reattempt communication at a later time. The MAX6876
generates a NACK after the slave address during a
software reboot, while writing to the EEPROM, or when
receiving an illegal memory address.
STOP
CONDITION
REPEATED START
CONDITION
START
CONDITION
tHIGH
tLOW
tR
tF
tSU:DAT
tSU:STA
tSU:STO
tHD:STA
tBUF
tHD:STA
tHD:DAT
SCL
SDA
START
CONDITION
Figure 10. Serial-Interface Timing Details
DATA LINE STABLE,
DATA VALID
SDA
SCL
CHANGE OF
DATA ALLOWED
Figure 11. Bit Transfer
P
S
START
CONDITION
SDA
SCL
STOP
CONDITION
Figure 12. Start and Stop Conditions
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