參數(shù)資料
型號(hào): MAX6875ETJ+T
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 電源管理
英文描述: EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors
中文描述: 4-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQCC32
封裝: 7 X 7 MM, TQFN-32
文件頁數(shù): 39/40頁
文件大?。?/td> 403K
代理商: MAX6875ETJ+T
MAX6874/MAX6875
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors
8
_______________________________________________________________________________________
Pin Description
PIN
MAX6874
MAX6875
NAME
FUNCTION
13
PO2
Programmable Output 2. Configurable active-high or active-low open-drain output. PO2 pulls
low with a 10A internal current sink for +1V < VABP < VUVLO. PO2 assumes its programmed
conditional output state when ABP exceeds UVLO.
25
PO3
Programmable Output 3. Configurable active-high or active-low open-drain output. PO3 pulls
low with a 10A internal current sink for +1V < VABP < VUVLO. PO3 assumes its programmed
conditional output state when ABP exceeds UVLO.
36
PO4
Programmable Output 4. Configurable active-high or active-low open-drain output. PO4 pulls
low with a 10A internal current sink for +1V < VABP < VUVLO. PO4 assumes its programmed
conditional output state when ABP exceeds UVLO.
44
GND
Ground
57
PO5
Programmable Output 5. Configurable active-high or active-low open-drain output. PO5 pulls
low with a 10A internal current sink for +1V < VABP < VUVLO. PO5 assumes its programmed
conditional output state when ABP exceeds UVLO.
6—
PO6
Programmable Output 6. Configurable active-high or active-low open-drain output. PO6 pulls
low with a 10A internal current sink for +1V < VABP < VUVLO. PO6 assumes its programmed
conditional output state when ABP exceeds UVLO.
7—
PO7
Programmable Output 7. Configurable active-high or active-low open-drain output. PO7 pulls
low with a 10A internal current sink for +1V < VABP < VUVLO. PO7 assumes its programmed
conditional output state when ABP exceeds UVLO.
8—
PO8
Programmable Output 8. Configurable active-high or active-low open-drain output. PO8 pulls
low with a 10A internal current sink for +1V < VABP < VUVLO. PO8 assumes its programmed
conditional output state when ABP exceeds UVLO.
9, 10, 23,
24
1, 8, 9,10,
16, 17,
23–26, 32
N.C.
No Connection. Not internally connected.
11
MARGIN
Margin Input. Drive MARGIN low to hold PO_ in their existing states. Leave MARGIN
unconnected or connect to DBP if unused. MARGIN overrides MR if both assert at the same
time. MARGIN is internally pulled up to DBP through a 10A current source.
12
MR
Manual Reset Input. MR to either assert PO_ into a programmed state or to have no effect on
PO_ when driving MR low (see Table 6). Leave MR unconnected or connect to DBP if unused.
MR is internally pulled up to DBP through a 10A current source.
13
SDA
Serial Data Input/Output (Open-Drain). SDA requires an external pullup resistor.
14
SCL
Serial Clock Input. SCL requires an external pullup resistor.
15
A0
Address Input 0. Address inputs allow up to four MAX6874 or two MAX6875 connections on
one common bus. Connect A0 to GND or to the serial interface power supply.
16
A1
Address Input 1 (MAX6874 only). Address inputs allow up to four MAX6874 connections on
one common bus. Connect A1 to GND or to the serial interface power supply.
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