參數(shù)資料
型號: MAX6852
廠商: Maxim Integrated Products, Inc.
英文描述: 4-Wire Interfaced, 5 x 7 Matrix Vacuum- Fluorescent Display Controller
中文描述: 4線接口、5 x 7點(diǎn)陣、真空熒光顯示控制器
文件頁數(shù): 16/32頁
文件大小: 489K
代理商: MAX6852
M
4-Wire Interfaced, 5
7 Matrix Vacuum-
Fluorescent Display Controller
16
______________________________________________________________________________________
between grids. Thus, image ghosting is avoided. If a
display has very slow phosphor, then the allowed decay
time can be doubled by not using a 15/16 duty cycle.
VFBLANK Polarity Register
The VFBLANK polarity register sets the active level of
the VFBLANK output pin (Table 26).
No-Op Register
A write to the no-op register is ignored.
Display-Test and Device ID Register
Writing the display-test and device ID register switches
the drivers between one of two modes: normal and dis-
play test. Display-test mode turns all segments and
annunciators on and sets the duty cycle to 7/16 (half-
power) (Table 27).
Reading the display-test and device ID register returns
the MAX6852 device ID 0b0000 011 that identifies the
driver type, plus the display-test status in the LSB.
Output Shift-Limit Register
The output serial interface is used to transfer display
data from the MAX6852 to the display driver. The serial
interface bit-stream output length is programmable up
to 122 bits, which are labeled DD0
DD121. Set the
number of bits with the shift-limit register, address
0x0E. If the shift-limit register is written with an out-of-
range value 0x7A to 0xFF, then the value 0x79 is stored
instead. Table 28 shows the shift-limit register.
Output Map
The output map comprises 122 words of 7-bit RAM.
The output map data should be written when the
MAX6852 is configured after power-up. Table 29 shows
the output map RAM codes.
t
VCL
t
VDS
t
VCH
t
VCP
t
VCSH
t
VCSW
VFCLK
VFLOAD
M (M IS VALUE IN SHIFT-LIMIT REGISTER)
VFDOUT
DD0
DD1
M-1
Figure 9. VFD Interface Timing Diagram
VFCLK
VFDOUT
VFLOAD
DD0
DD1
DD2
DD3
DD4
DD5
DD6 DD7
DD8
DD9 DD10
M-4
M-3
M-2
M-1
M
(M IS VALUE IN SHIFT-LIMIT REGISTER)
GRID 1's DATA, SENT DURING GRID 0's TIMESLOT
GRID 0's 100
μ
s MULTIPLEX TIMESLOT
ONE COMPLETE MULTIPLEX CYCLE AROUND N GRIDS (OSC = 4MHz)
START OF NEXT
CYCLE
500ns
500ns
500ns 500ns
100
μ
s TIMESLOT
GRID 0
100
μ
s TIMESLOT
GRID 1
100
μ
s TIMESLOT
GRID N-4
100
μ
s TIMESLOT
GRID N-3
100
μ
s TIMESLOT
GRID N-2
100
μ
s TIMESLOT
GRID N-1
100
μ
s TIMESLOT
GRID 0
Figure 10. VFD Multiplex Timing Diagram
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