參數(shù)資料
型號: MAX6852
廠商: Maxim Integrated Products, Inc.
英文描述: 4-Wire Interfaced, 5 x 7 Matrix Vacuum- Fluorescent Display Controller
中文描述: 4線接口、5 x 7點陣、真空熒光顯示控制器
文件頁數(shù): 13/32頁
文件大?。?/td> 489K
代理商: MAX6852
M
4-Wire Interfaced, 5
7 Matrix Vacuum-
Fluorescent Display Controller
______________________________________________________________________________________
13
Control and Operation Using the 4-Wire
Interface
Controlling the MAX6852 requires sending a 16-bit
word. The first byte, D15 through D8, is the command
address, and the second byte, D7 through D0, is the
data to be written to the command address (Table 23).
Connecting Multiple MAX6852s to the
4-Wire Bus
Daisy-chain multiple MAX6852s by connecting the
DOUT of one device to the DIN of the next, and driving
SCLK and
CS
lines in parallel. Data at DIN propagates
through the internal shift registers and appears at
DOUT 15.5 clock cycles later, clocked out on the rising
edge of SCLK. When sending commands to daisy-
chained MAX6852s, all devices are accessed at the
same time. An access requires (16 x n) clock cycles,
where n is the number of MAX6852s connected togeth-
er. To update just one device in a daisy-chain, send the
no-op command (0x00) to the others. Care must be
taken on power-up when daisy-chaining the serial inter-
face in this manner. Configure each MAX6852
s PORT0
or PORT1 outputs, in turn, to act as DOUT before data
propagates through it. For this reason, PORT0 is the
preferred output to configure as DOUT because its out-
put on power-up is low. This means that a daisy-
chained DIN input taking data from an uninitialized
PORT0 output clocks in 16 logic zeros, which is the
safe no-op instruction.
Writing Device Registers
The MAX6852 contains a 16-bit shift register into which
DIN is clocked on the rising edge of SCLK, when
CS
is
low. When
CS
is high, transitions on SCLK have no
effect. When
CS
goes high, the 16 bits in the shift regis-
ter are parallel loaded into a 16-bit latch. The 16 bits in
the latch are then decoded and executed.
The MAX6852 is written to using the following
sequence:
1) Take SCLK low.
2) Take
CS
low. This enables the internal 16-bit shift
register.
3) Clock 16 bits of data into DIN, D15 first to D0 last,
observing the setup and hold times. Bit D15 is low,
indicating a write command.
4) Take
CS
high (while SCLK is still high after clocking
in the last data bit).
5) Take SCLK low.
Figure 7 shows a write operation when 16 bits are
transmitted.
RAM15
RAM14
RAM13
RAM12
RAM11
RAM10
RAM09
RAM08
RAM07
RAM05
RAM04
RAM03
RAM02
RAM01
RAM00
RAM16
RAM17
RAM18
RAM19
RAM20
RAM21
RAM23
1111
1110
1101
1100
1011
1010
1001
1000
0111
RAM06
RAM22
0110
0101
0100
0011
0010
0001
0000
MSB
LSB
x000
x001
x010
x011
x100
x101
x110
x111
Table 7. Character Map
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