參數(shù)資料
型號: MAX6851AEE-T
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 顯示控制器
英文描述: 2-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
中文描述: FLUORESCENT DSPL CTRL, PDSO16
封裝: 0.150 INCH, 0.635 MM PITCH, QSOP-16
文件頁數(shù): 24/37頁
文件大?。?/td> 493K
代理商: MAX6851AEE-T
MAX6851
2-Wire Interfaced, 7-, 14-, and 16-Segment Alpha-
numeric Vacuum-Fluorescent Display Controller
30
______________________________________________________________________________________
The PWM duty cycle is controlled by the filament duty-
cycle register (Table 38). The effective RMS voltage
across the filament is given by the expression:
VRMS = FilOn x (VFIL - VLO-BRIDGE - VHI-BRIDGE) / 200
or, rearranged:
Duty = 200 x VRMS / (VFIL - VLO-BRIDGE - VHI-BRIDGE)
where:
FilOn is the number to store in the filament duty-cycle
register, address 0x09.
VFIL is the supply voltage to the filament driver bridge (V).
VRMS is the specified nominal filament supply voltage (V).
VLO-BRIDGE is the voltage drop across a low-side
bridge driver (V).
VHI-BRIDGE is the voltage drop across a high-side
bridge driver (V).
The minimum commutation time, shown at (C) in Figure
19, is set by (2/OSC)s (500ns when OSC = 4MHz) to
ensure that shoot-through currents cannot flow during
phase reversal. Otherwise, the duty cycle of the bridge
(total on-time: total time) sets the RMS voltage across
the filament. This technique provides a low-cost AC fila-
ment supply when using a regulated supply higher than
the RMS voltage rating of the filament.
Figure 20 shows the external components required for
the filament driver using a FET bridge.
PHASE1 and PHASE2 Outputs
PHASE1 and PHASE2 can be individually programmed
as one of four output types (Tables 39, 40).
When using the filament drive, first ensure that the fila-
ment duty-cycle register 0x09 is set to the correct value
before configuring the PHASE1 and PHASE2 outputs to
be filament drives. To stop the filament drive, program
either PHASE1 or PHASE2 (or both) to be logic-low gen-
eral-purpose outputs. Both PHASE1 and PHASE2 out-
puts come out of power-on-reset in logic-low condition.
PUMP Output
The PUMP output can be programmed as one of four
output types (Table 41).
PORT0 and PORT1 Outputs
PORT0 and PORT1 can be individually programmed as
one of eight output types (Tables 42, 43). The PORT1
choices are similar to the PORT0 choices, except that
the last four items are invert logic. PORT0 output comes
out of power-on-reset in logic-low condition, whereas
PORT1 output initializes high.
The PORT0 and PORT1 shutdown outputs allow exter-
nal hardware (for example, a DC-to-DC converter
power supply for VFD) to be disabled by the MAX6851
when the MAX6851 is shut down.
The 625Hz, 1250Hz, and 2500Hz outputs can drive a
piezo sounder either from PORT0 or PORT1 alone, or
by both ports together as bridge drive. For bridge
drive, the sounder is connected between PORT0 and
PORT1, taking advantage of the PORT1 output being
inverted with respect to PORT0. Select different fre-
quencies for PORT0 and PORT1 to obtain a wider
range of sounds when bridge drive is used.
Multiplex Clock and Blink Timing
The OSC1 and OSC2 inputs set the multiplex and blink
timing for the display driver. Connect an external resis-
tor from OSC2 to GND and an external capacitor COSC
from OSC1 to GND to set the frequency of the internal
RC oscillator. Alternatively, overdrive OSC1 with an
external TTL or CMOS clock. If an exact blink rate or
multiplex period is required, use an external clock
ranging between 2MHz and 8MHz to drive OSC1.
(A)
(B)
(C)
(D)
(E)
100
s MULTIPLEX TIME PERIOD (OSC = 4MHz)
PHASE 1
PHASE 2
Figure 19. Filament Bridge Driver Timing Waveforms
R2
R4
Q2
Q1
GND
Q3
Q4
PHASE 1
PHASE 2
VFIL
VFD TUBE
GND
Figure 20. Filament Bridge Driver (MOSFET)
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