參數(shù)資料
型號: MAX6851AEE-T
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 顯示控制器
英文描述: 2-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
中文描述: FLUORESCENT DSPL CTRL, PDSO16
封裝: 0.150 INCH, 0.635 MM PITCH, QSOP-16
文件頁數(shù): 22/37頁
文件大?。?/td> 493K
代理商: MAX6851AEE-T
MAX6851
2-Wire Interfaced, 7-, 14-, and 16-Segment Alpha-
numeric Vacuum-Fluorescent Display Controller
______________________________________________________________________________________
29
OUTPUT MAP RAM
CONTENT
ADDRESS RANGE
ADDRESSED FUNCTION
82 to 85
4 annunciators
Only valid for 48/1 mode
(display mode select bit M = 0)
Annunciator A1 to annunciator A4
86
Cursor
Cursor segment for digits 0 to 47 on 1st row
87
Cursor
Only valid for 96/2 mode
(display mode select bit M = 1)
Cursor segment for digits 0 to 47 on 2nd row
88 to 127
Unused
No action
Table 32. Output Map RAM Codes (continued)
The power-up default pattern for output map RAM
maps a 40-digit, two-digits-per-grid display with DPs
and cursors (Table 33).
If the user selects an unused map RAM entry (88–127)
for an output shift-register position, then the correspond-
ing output bit is always low (segment or grid OFF).
When selecting an invalid map RAM entry (for example,
codes 48 to 83 to select annunciators in 96/2 mode,
which does not support annunciators), the correspond-
ing output bit is always low (segment or grid OFF).
If the map RAM entry corresponds to a nonexistent font
segment (no action in Table 33) when the digit data is
processed through the character font, then the result
again is zero (segment or grid OFF).
The output map data is indirectly accessed by an
autoincrementing output map address pointer in the
MAX6851 at address 0x06. The output map address
pointer can be written (i.e., set to an address between
0x00 and 0x53) but cannot be read back. The output
map data is written and read back through the output
map address pointer.
Table 34 shows how to set the output map address
pointer to a value within the acceptable range. Bit D7 is
set to denote that the user is writing the output map
address pointer. If the user attempts to set the output
map address to one of the out-of-range addresses by
writing data in range 0xD4 to 0xFF, then address 0x00
is set instead.
After the last data location 0x53 has been written, fur-
ther output map data entries are ignored until the out-
put map address pointer is reset.
The output map data can be written to the address set
by the output map address pointer. Bit D7 is clear to
denote that the user is writing actual output map data.
The output map address pointer is autoincremented
after the output map data has been written to the cur-
rent location. If the user writes the output map data in
the RAM order, then the output map address pointer
need only be set once, or even not at all as the address
is set to 0x00 as power-up default (Table 35).
The output map data can be read by reading address
0x86. The 7-bit output map data at the address set by the
output map address pointer is read back, with the MSB
clear. The output map address pointer is autoincrement-
ed after the output map data has been read from the cur-
rent location, in the same way as for a write (Table 36).
Filament Drive
The VFD filament is typically driven with an AC wave-
form, supplied by a center-tapped 50Hz or 60Hz power
transformer as part of the system power supply.
However, if the system has only DC supplies available,
the filament must be powered by a DC-to-AC or DC-to-
DC converter.
The MAX6851 can generate the waveforms on the
PHASE1 and PHASE2 outputs to drive the VFD filament
using a full bridge (push-pull drive). The PHASE1 and
PHASE2 outputs can be used as general-purpose out-
puts if the filament drive is not required. The bridge
drive transistors are external, but the waveforms are
generated by the MAX6851.
The waveform generation uses PWM to set the effective
RMS voltage across the filament, as a fraction of the
external supply voltage (Figure 19) (Table 37). The fila-
ment switching frequency is synchronized to the multi-
plex scan clock, eliminating beating artifacts due to
differing filament and multiplex frequencies.
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