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參數(shù)資料
| 型號： | MAX5913 |
| 廠商： | Maxim Integrated Products, Inc. |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | +48V Quad Hot-Swap Controllers For Power-Over-LAN |
| 中文描述： | +48V、四路、熱插拔控制器，用于LAN供電 |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 827K |
| 代理商： | MAX5913 |
M
+48V Quad Hot-Swap Controllers For
Power-Over-LAN
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= V
CSP
_ = +48V, AGND = DGND = 0, V
DD
= +3.3V, V
RLY
= +12V, T
A
= -40
°
C to +85
°
C, unless otherwise noted. Typical values
are at V
CC
= V
CSP
_ = +48V and T
A
= +25
°
C.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
During current regulation
V
ON
= 0
Gate Discharge Current
I
GATE
,
DIS
(V
CSP
_ - V
DRAIN
_) > V
FC
V
OUT
_ = 0, force 30mA into GATE_, measure
V
GATE
- V
OUT
OPEN-CIRCUIT DETECTOR
Note 1:
See
Typical Operating Characteristics
for Current-Limit Foldback, and refer to
Current Sensing and Regulation
section.
Note 2:
The resistor at RTIM can range from 2k
to 40k
.
Note 3:
Limits are 100% tested at T
A
= +25
°
C and T
A
= +85
°
C. Limits at -40
°
C are guaranteed by design and characterization, but
are not production tested.
MIN
TYP
8
1
15
MAX
UNITS
μA
mA
mA
Source-Gate Clamp Voltage
V
SGZ
14
16.5
18
V
Open-Circuit Current-Threshold
Voltage
V
OC
Minimum
V across R
SENSE
to detect an
open circuit
1.5
3
4.5
mV
Delay to Open-Circuit Detect
Deglitch Delay
RELAY DRIVERS
Maximum Low Voltage (MAX5913)
Relay Pullup Current (MAX5914)
t
OC
t
LPFD
(Figure 2)
(V
CSP
_ - V
DRAIN
__
) < V
OC
(Figure 2)
450
106
900
204
1350
302
ms
ms
V
RLOW
I
RPLUP
RLYON = high, I
RLYD
_ = 100mA
RLYON = high, V
RLYD
_ = 0
Force 100mA into RLYD, measure V
RLYD
-
V
RLY
RLYON_ = low, V
RLYD
_ = V
RLY
0.5
1.3
V
0.3
0.8
mA
Clamp Diode Voltage
V
RCLAMP
2
V
Relay Output Leakage
TIMING
1
μA
R
RTIM
= 2k
R
RTIM
= 40k
R
RTIM
=
∞
4.8
76
3.2
6.4
128
6.4
1
2
4
25.6
3.2
8.0
180
9.6
Short-Circuit and Startup Timer
(Note 2)
t
O
On time for continuous
overcurrent conditions
ms
DC = logic low
DC = logic high
DC = floating
V
ON
= 3.3V (Figure 3)
After RLYON_ goes low (Figure 3)
Auto-Retry Duty Cycle
%
Port Turn-ON Delay
Relay Turn-OFF Delay
DIGITAL INTERFACE
DC Pin Input Voltage High
DC Pin Input Voltage Low
DC Pin Input Impedance
Logic Input High
Logic Input Low
Logic Input Leakage
FAULT
Output Voltage Low
FAULT
High Input Leakage
Logic Output Voltage High
Logic Output Voltage Low
t
ON
_
DEL
t
OFF
_
DEL
12.8
1.6
38.4
4.8
ms
ms
V
IH
_
DC
V
IL
_
DC
+1.8V
≤
V
DD
≤
+3.7V
+1.8V
≤
V
DD
≤
+3.7V
0.7 x V
DD
V
V
0.3 x V
DD
R
IN
_
DC
V
IH
V
IL
1
k
V
V
μA
V
μA
mV
V
+1.8V
≤
V
DD
≤
+3.7V
+1.8V
≤
V
DD
≤
+3.7V
0.8 x V
DD
0.3 x V
DD
1
V
FL
I
SINK
= 4mA
0.4
1
V
OH
V
OL
STAT_ outputs sourcing 0.5mA
STAT_ outputs sinking 0.5mA
V
DD
- 0.4
0.4
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