參數(shù)資料
型號(hào): MAX5889EGK+D
廠商: Maxim Integrated Products
文件頁數(shù): 4/16頁
文件大?。?/td> 0K
描述: IC DAC 12BIT LVDS 600MSPS 68-QFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 30
設(shè)置時(shí)間: 11ns
位數(shù): 12
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字
功率耗散(最大): 297mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 68-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 68-QFN 裸露焊盤(10x10)
包裝: 管件
輸出數(shù)目和類型: 2 電流,單極
采樣率(每秒): 600M
MAX5889
Grounding, Bypassing, and Power-Supply
Considerations
Grounding and power-supply decoupling strongly influ-
ence the MAX5889 performance. Unwanted digital
crosstalk coupling through the input, reference, power
supply, and ground connections affects dynamic per-
formance. High-speed, high-frequency applications
require closely followed proper grounding and power-
supply decoupling. These techniques reduce EMI and
internal crosstalk that can significantly affect the
MAX5889 dynamic performance.
Use a multilayer printed circuit (PC) board with sepa-
rate ground and power-supply planes. Run high-speed
signals on lines directly above the ground plane. Keep
digital signals as far away from sensitive analog inputs
and outputs, reference input sense lines, common-
mode inputs, and clock inputs as practical. Use a sym-
metric design of clock input and the analog output lines
to minimize 2nd-order harmonic distortion components,
thus optimizing the DAC’s dynamic performance. Keep
digital signal paths short and run lengths matched to
avoid propagation delay and data skew mismatches.
The MAX5889 requires five separate power-supply
inputs for analog (AVDD1.8 and AVDD3.3), digital
(DVDD1.8 and DVDD3.3), and clock (AVCLK) circuitry.
Decouple each AVDD3.3, AVDD1.8, AVCLK, DVDD3.3, and
DVDD1.8 input with a separate 0.1F capacitor as close
to the device as possible with the shortest possible con-
nection to the respective ground plane (Figure 7).
Connect all the 3.3V supplies together at one point with
ferrite beads to minimize supply noise coupling.
Decouple all five power-supply voltages at the point they
enter the PC board with tantalum or electrolytic capaci-
tors. Ferrite beads with additional decoupling capacitors
forming a pi network can also improve performance.
Similarly, connect all 1.8V supplies together at one point
with ferrite beads.
The analog and digital power-supply inputs AVDD3.3,
AVCLK, and DVDD3.3 allow a 3.135V to 3.465V supply
voltage range. The analog and digital power-supply
inputs AVDD1.8 and DVDD1.8 allow a 1.71V to 1.89V
supply voltage range.
The MAX5889 is packaged in a 68-pin QFN-EP pack-
age with exposed paddle, providing optimized DAC AC
performance. The exposed pad must be soldered to
the ground plane of the PC board. Thermal efficiency is
not the key factor, since the MAX5889 features low-
power operation. The exposed pad ensures a solid
ground connection between the DAC and the PC
board’s ground layer.
The data converter die attaches to an EP lead frame
with the back of this frame exposed at the package
bottom surface, facing the PC board side of the pack-
age. This allows for a solid attachment of the package
to the PC board with standard infrared (IR) reflow sol-
dering techniques. A specially created land pattern on
the PC board, matching the size of the EP (6mm x
6mm), ensures the proper attachment and grounding of
the DAC. Place vias into the land area and implement
12-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
12
______________________________________________________________________________________
MAX5889
OUTP
OUTN
AGND
25
50
25
OUTP
OUTN
D0–D11
LVDS
DATA INPUTS
Figure 6. Differential Output Configuration
MAX5889
OUTP
AVDD3.3
AVDD1.8
DVDD3.3
DVDD1.8
AVCLK
OUTN
0.1F
3.3V VOLTAGE SUPPLY
0.1F
1.8V VOLTAGE SUPPLY
0.1F
BYPASSING—DAC LEVEL
*FERRITE BEADS
D0–D11
LVDS
DATA INPUTS
*
**
Figure 7. Recommended Power-Supply Decoupling and
Bypassing Circuitry
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