參數(shù)資料
型號(hào): MAX5889EGK+D
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 15/16頁(yè)
文件大?。?/td> 0K
描述: IC DAC 12BIT LVDS 600MSPS 68-QFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 30
設(shè)置時(shí)間: 11ns
位數(shù): 12
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字
功率耗散(最大): 297mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 68-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 68-QFN 裸露焊盤(10x10)
包裝: 管件
輸出數(shù)目和類型: 2 電流,單極
采樣率(每秒): 600M
MAX5889
12-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
8
_______________________________________________________________________________________
PIN
NAME
FUNCTION
1, 46, 48, 50,
52, 54, 56, 58,
60, 63, 65, 67
D0N, D11N, D10N,
D9N, D8N, D7N,
D6N, D5N, D4N,
D3N, D2N, D1N
Differential Negative LVDS Inputs. Data bits D0–D11 (offset binary format).
2–9
N.C.
No Connection. Leave floating or connect to DGND.
10
DGND
Digital Ground. Ground return for DVDD3.3 and DVDD1.8.
11
DVDD3.3
Digital Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a
0.1F capacitor to DGND.
12
PD
Power-Down Input. Set PD high to force the DAC into power-down mode. Set PD low for
normal operation. PD has an internal 2A pulldown.
13, 42, 43, 44
N.C.
No Connection. Leave floating or connect to AGND.
14, 21, 22, 25,
26, 31, 32
AVDD3.3
Analog Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a
0.1F capacitor to AGND.
15, 20, 23, 24,
27, 30, 33
AGND
Analog Ground. Ground return for AVDD3.3 and AVDD1.8.
16
REFIO
Reference I/O. Output of the internal 1.2V precision bandgap reference. Bypass with a
0.1F capacitor to AGND. REFIO can be driven with an external reference source.
17
FSADJ
Full-Scale Current Adjustment. Connect an external resistor RSET between FSADJ and
DACREF to set the output full-scale current. The output full-scale current is equal to 32 x
VREF / RSET.
18
DACREF
Current-Set Resistor Return Path. Internally connected to ground, but do not use as
ground connection.
19, 34, 35
AVDD1.8
Analog Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass with a
0.1F capacitor to AGND.
28
OUTN
Complementary DAC Output. Negative terminal for current output.
29
OUTP
DAC Output. Positive terminal for current output.
36, 41
AVCLK
Clock Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a
0.1F capacitor to CGND.
37, 40
CGND
Clock Supply Ground
38
CLKN
Complementary Converter Clock Input. Negative input terminal for differential converter
clock.
39
CLKP
Converter Clock Input. Positive input terminal for differential converter clock.
45, 47, 49, 51,
53, 55, 57, 59,
62, 64, 66, 68
D11P, D10P, D9P,
D8P, D7P, D6P, D5P,
D4P, D3P, D2P, D1P,
D0P
Differential Positive LVDS Inputs. Data bits D0–D11 (offset binary format).
61
DVDD1.8
Digital Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass with a
0.1F capacitor to DGND.
—EP
Exposed Pad. Must be connected to common point for AGND, DGND, and CGND through
a low-impedance path. EP is internally connected to AGND, DGND, and CGND.
Pin Description
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