參數(shù)資料
型號(hào): MAX5888EGK
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi): DAC
英文描述: 3.3V, 16-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs
中文描述: PARALLEL, WORD INPUT LOADING, 0.011 us SETTLING TIME, 16-BIT DAC, QCC68
封裝: 10 X 10 MM, 0.9 MM HEIGHT, MO-220, QFN-68
文件頁(yè)數(shù): 7/18頁(yè)
文件大小: 746K
代理商: MAX5888EGK
M
3.3V, 16-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
_______________________________________________________________________________________
7
Pin Description
PIN
1
2
3
4
5
6
7
8
NAME
B3P
B3N
B2P
B2N
B1P
B1N
B0P
B0N
DGND
FUNCTION
Data Bit 3
Complementary Data Bit 3
Data Bit 2
Complementary Data Bit 2
Data Bit 1
Complementary Data Bit 1
Data Bit 0 (LSB)
Complementary Data Bit 0 (LSB)
Digital Ground
9, 41, 60, 62
10, 40, 61
DV
DD
Digital Supply Voltage. Accepts a supply voltage range of 3.135V to 3.465V. Bypass each pin with a
0.1μF capacitor to the nearest DGND.
11, 16
VCLK
Clock Supply Voltage. Accepts a supply voltage range of 3.135V to 3.465V. Bypass each pin with a
0.1μF capacitor to the nearest CLKGND.
12, 15
13
14
CLKGND
CLKP
CLKN
Clock Ground
Converter Clock Input. Positive input terminal for the differential converter clock.
Complementary Converter Clock Input. Negative input terminal for the differential converter clock.
17
PD
Power-Down Input. PD pulled high enables the DAC
s power-down mode. PD pulled low allows for
normal operation of the DAC. This pin features an internal pulldown resistor.
18, 24, 29,
30, 32
AV
DD
Analog Supply Voltage. Accepts a supply voltage range of 3.135V to 3.465V. Bypass each pin with a
0.1μF capacitor to the nearest AGND.
19, 25, 28,
31, 33, EP
AGND
Analog Ground. Exposed paddle (EP) must be connected to AGND.
20
REFIO
Reference I/O. Output of the internal 1.2V precision bandgap reference. Bypass with a 1μF capacitor
to AGND. Can be driven with an external reference source.
21
FSADJ
Full-Scale Adjust Input. This input sets the full-scale output current of the DAC. For 20mA full-scale
output current, connect a 2k
resistor between FSADJ and DACREF.
22
DACREF
Return Path for the Current Set Resistor. For 20mA full-scale output current, connect a 2k
resistor
between FSADJ and DACREF.
23, 34
38
N.C.
Not Connected.
Do not connect to these pins. Do not tie these pins together.
26
IOUTN
Complementary DAC Output. Negative terminal for differential current output. The full-scale output
current range can be set from 2mA to 20mA.
27
IOUTP
DAC Output. Positive terminal for differential current output. The full-scale output current range can
be set from 2mA to 20mA.
39
SEL0
Mode Select Input SEL0. Set high to activate the segment shuffling function. Since this pin features an
internal pulldown resistor, it can be left open or pulled low to disable the segment-shuffling function.
See
Segment Shuffling
in the
Detailed Description
section for more information.
42
43
44
B15P
B15N
B14P
Data Bit 15 (MSB)
Complementary Data Bit 15 (MSB)
Data Bit 14
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