參數(shù)資料
型號(hào): MAX5888EGK
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: DAC
英文描述: 3.3V, 16-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs
中文描述: PARALLEL, WORD INPUT LOADING, 0.011 us SETTLING TIME, 16-BIT DAC, QCC68
封裝: 10 X 10 MM, 0.9 MM HEIGHT, MO-220, QFN-68
文件頁(yè)數(shù): 4/18頁(yè)
文件大?。?/td> 746K
代理商: MAX5888EGK
M
3.3V, 16-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= DV
DD
= VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference, V
REFIO
= 1.25V, differential transformer-coupled
analog output, 50
double terminated (Figure 7), I
OUT
= 20mA, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
+25
°
C guaranteed by
production test, <+25
°
C guaranteed by design and characterization. Typical values are at T
A
= +25
°
C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS
Data to Clock Setup Time
Data to Clock Hold Time
t
SETUP
t
HOLD
Referenced to rising edge of clock (Note 4)
Referenced to rising edge of clock (Note 4)
-0.8
1.8
ns
ns
Data Latency
3.5
Clock
cycles
ns
ns
Minimum Clock Pulse Width High
Minimum Clock Pulse Width Low
LVDS LOGIC INPUTS (B0N–B15N, B0P–B15P)
Differential Input Logic High
Differential Input Logic Low
Common-Mode Voltage Range
Differential Input Resistance
Input Capacitance
CMOS LOGIC INPUTS (PD, SEL0)
t
CH
t
CL
CLKP, CLKN
CLKP, CLKN
0.9
0.9
V
IH
V
IL
V
COM
R
IN
C
IN
100
mV
mV
V
pF
-100
1.375
125
1.125
85
100
5
Input Logic High
V
IH
0.7
DV
DD
V
Input Logic Low
V
IL
0.3
DV
DD
+15
V
Input Leakage Current
Input Capacitance
CLOCK INPUTS (CLKP, CLKN)
I
IN
C
IN
-15
μA
pF
5
Sine wave
Square wave
(Note 5)
1.5
0.5
>100
Differential Input Voltage Swing
V
CLK
V
P-P
Differential Input Slew Rate
SR
CLK
V/μs
Common-Mode Voltage Range
V
COM
1.5
±20%
V
Input Resistance
Input Capacitance
POWER SUPPLIES
Analog Supply Voltage Range
Digital Supply Voltage Range
Clock Supply Voltage Range
R
CLK
C
CLK
5
5
k
pF
AV
DD
DV
DD
V
CLK
3.135
3.135
3.135
3.3
3.3
3.3
27
0.3
7
10
5.6
10
3.465
3.465
3.465
V
V
V
f
CLK
= 100Msps, f
OUT
= 1MHz
Power-down
f
CLK
= 100Msps, f
OUT
= 1MHz
Power-down
f
CLK
= 100Msps, f
OUT
= 1MHz
Power-down
Analog Supply Current
I
AVDD
mA
mA
μA
mA
μA
Digital Supply Current
I
DVDD
Clock Supply Current
I
VCLK
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