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參數(shù)資料
| 型號(hào)： | MAX5858ECM+TD |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 10/23頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 10BIT DUAL 300MSPS 48TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 設(shè)置時(shí)間： | 11ns |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 816mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP 裸露焊盤（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電流，單極 |
| 采樣率（每秒）： | 300M |
MAX5858
Dual, 10-Bit, 300Msps, Current-Output DAC with
4x/2x/1x Interpolation Filters
18
______________________________________________________________________________________
The MAX5858 can also operate in an interleave data
mode. Pulling IDE high activates this mode. In inter-
leave mode, data for both DAC channels is written
through input port A. Channel B data is written on the
falling edge of the CLK signal and then channel A data
is written on the following rising edge of the CLK signal.
Both DAC outputs (channel A and B) are updated
simultaneously on the next following rising edge of the
CLK. In interleave data mode, the maximum input data
rate per channel is half of the rate in noninterleave
mode. The interleave data mode is attractive in applica-
tions where lower data rates are acceptable and inter-
facing on a single 10-bit bus is desired (Figure 7).
Applications Information
Differential-to-Single-Ended Conversion
The MAX5858 exhibits excellent dynamic performance
to synthesize a wide variety of modulation schemes,
including high-order QAM modulation with OFDM.
Figure 8 shows a typical application circuit with output
transformers performing the required differential-to-sin-
gle-ended signal conversion. In this configuration, the
MAX5858 operates in differential mode, which reduces
even-order harmonics, and increases the available out-
put power.
F2EN
F1EN
DIFFERENTIAL CLOCK
FREQUENCY (fCLKDIFF) (MHz)
CLK OUTPUT
(MHz)
DAC RATE
(fDAC)
INTERPOLATION
MAX SIGNAL
BANDWIDTH (MHz)
0
0 to 165
FCLKDIFF
fCLKDIFF
1x
82
0
1
0 to 300
FCLKDIFF/2
fCLKDIFF
2x
63
1
0 to 300
fCLKDIFF/4
fCLKDIFF
4x
31
1
0
Illegal
Table 5. Clocking Modes
IFS
0.1
F
10
F
AVDD
RSET
IREF
REFR
AVDD
REFO
1.24V
BANDGAP
REFERENCE
CURRENT-
SOURCE ARRAY
EXTERNAL
+1.24V
REFERENCE
REN
MAX5858
MAX6520
AGND
Figure 5. MAX5858 with External Reference
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