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參數(shù)資料
| 型號： | MAX5852ETL+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 5/18頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 8BIT DUAL 165MSPS 40-TQFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 設(shè)置時間： | 12ns |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 40-TQFN-EP（6x6） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電流，單極 |
| 采樣率（每秒）： | 200M |
MAX5852
Dual, 8-Bit, 165Msps, Current-Output DAC
______________________________________________________________________________________
13
The CLK pin now becomes an output, and provides a
single-ended replica of the differential clock signal,
which may be used to synchronize the input data. Data is
written to the device on the rising edge of the CLK signal.
Internal Reference and Control Amplifier
The MAX5852 provides an integrated 50ppm/°C, 1.24V,
low-noise bandgap reference that can be disabled and
overridden with an external reference voltage. REFO
serves either as an external reference input or an inte-
grated reference output. If REN =0, the internal refer-
ence is selected and REFO provides a 1.24V (50A)
output. Buffer REFO with an external amplifier, when
driving a heavy load.
The MAX5852 also employs a control amplifier
designed to simultaneously regulate the full-scale out-
put current (IFS) for both outputs of the devices.
Calculate the output current as:
IFS = 32 IREF
where IREF is the reference output current (IREF =
VREFO / RSET) and IFS is the full-scale output current.
RSET is the reference resistor that determines the
amplifier output current of the MAX5852 (Figure 3). This
current is mirrored into the current-source array where
IFS is equally distributed between matched current seg-
ments and summed to valid output current readings for
the DACs.
External Reference
To disable the internal reference of the MAX5852, set
REN = 1. Apply a temperature-stable, external reference
to drive the REFO pin and set the full-scale output
(Figure 4). For improved accuracy and drift perfor-
mance, choose a fixed-output voltage reference such as
the 1.2V, 25ppm/°C MAX6520 bandgap reference.
Detailed Timing
The MAX5852 accepts an input data and the DAC con-
version rate of up to 165Msps. The input latches on the
rising edge of the clock, whereas the output latches on
the following rising edge.
Figure 5 depicts the write cycle of the two DACs in non-
interleaved mode.
The MAX5852 can also operate in an interleaved data
mode. Programming the IDE bit with a high level activates
this mode (Tables 1 and 2). In interleaved mode, data for
both DAC channels is written through input port A.
Channel B data is written on the falling edge of the clock
signal and then channel A data is written on the following
rising edge of the clock signal. Both DAC outputs (chan-
nel A and B) are updated simultaneously on the next fol-
lowing rising edge of the clock. In interleaved data mode,
the maximum input data rate per channel is half of the
rate in noninterleaved mode. The interleaved data mode
is attractive for applications where lower data rates are
acceptable and interfacing on a single 8-bit bus is
desired (Figure 6).
IFS
CCOMP*
REFR
IREF
REFO
MAX4040
1.24V
BANDGAP
REFERENCE
CURRENT-
SOURCE
ARRAY
*COMPENSATION CAPACITOR (CCOMP ≈ 100nF)
OPTIONAL EXTERNAL BUFFER
FOR HEAVIER LOADS
MAX5852
IREF =
VREF
RSET
AGND
REN = 0
Figure 3. Setting IFS with the Internal 1.24V Reference and the
Control Amplifier
AVDD
EXTERNAL
1.2V
REFERENCE
MAX6520
AGND
0.1F
10F
AVDD
AGND
IFS
REFR
IREF
REFO
1.24V
BANDGAP
REFERENCE
CURRENT-
SOURCE
ARRAY
MAX5852
RSET
AGND
REN = 1
Figure 4. MAX5852 with External Reference
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