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參數(shù)資料
| 型號(hào)： | MAX5852ETL+T |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 4/18頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8BIT DUAL 165MSPS 40-TQFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 設(shè)置時(shí)間： | 12ns |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 40-TQFN-EP（6x6） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電流，單極 |
| 采樣率（每秒）： | 200M |
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MAX5852
Dual, 8-Bit, 165Msps, Current-Output DAC
12
______________________________________________________________________________________
Device Power-Up and
States of Operation
At power-up, the MAX5852’s default configuration is
internal reference, noninterleaved input mode with a gain
of 0dB and a fully operational converter. In shutdown,
the MAX5852 consumes only 1A of supply current, and
in standby the current consumption is 3.1mA. Wake-up
time from standby mode to normal operation is 3s.
Clock Modes
The MAX5852 allows both single-ended CMOS and dif-
ferential clock mode operation, and supports update
rates of up to 165Msps. These modes are selected
through an active-low control line called DCE. In single-
ended clock mode (DCE = 1), the CLK pin functions as
an input, which accepts a user-provided single-ended
clock signal. Data is written to the converter on the rising
edge of the clock. The DAC outputs (previous data) are
updated simultaneously on the same edge.
If the DCE pin is pulled low, the MAX5852 will operate in
differential clock mode. In this mode, the clock signal has
to be applied to differential clock input pins
CLKXP/CLKXN. The differential input accepts an input
range of ≥0.5VP-P and a common-mode range of 1V to
(CVDD - 0.5V), making the part ideal for low- input ampli-
tude clock drives. CLKXP/CLKXN also help to minimize
the jitter, and allow the user to connect a crystal oscillator
directly to MAX5852.
CONTROL WORD
FUNCTION
PD
Power-Down. The part enters power-down mode if PD = 1.
DACEN
DAC Enable. When DACEN = 0 and PD = 0, the part enters standby mode.
IDE
Interleaved Data Mode. IDE = 1 enables the interleaved data mode. In this mode, digital data for both
channels is applied through channel A in a multiplexed fashion. Channel B data is written on the falling edge
of the clock signal and channel A data is written on the rising edge of the clock signal.
REN
Reference Enable Bit. REN = 0 activates the internal reference. REN = 1 disables the internal reference and
requires the user to apply an external reference between 0.1V to 1.32V.
G3
Bit 3 (MSB) of Gain Adjust Word
G2
Bit 2 of Gain Adjust Word
G1
Bit 1 of Gain Adjust Word
G0
Bit 0 (LSB) of Gain Adjust Word
Table 1. Control Word Format and Function
MODE
PD
DACEN
IDE
REN
Normal operation;
noninterleaved inputs;
internal reference active
01
0
Normal operation;
noninterleaved inputs;
internal reference disabled
01
0
1
Normal operation;
interleaved inputs; internal
reference disabled
01
1
Standby
0
X
Power-down
1
X
Power-up
0
1
X
Table 2. Configuration Modes
GAIN ADJUSTMENT ON
CHANNEL A (dB)
G3
G2
G1
G0
+0.4
0000
0
1000
-0.35
1111
Table 3. Gain Difference Setting
X = Don’t care.
MSB
LSB
PD
DACEN
IDE
REN
G3
G2
G1
G0
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