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參數(shù)資料
| 型號： | MAX5774UTK+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 11/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT 32CH V-OUT 68-TQFN |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 設置時間： | 20µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 32 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-TQFN 裸露焊盤 |
| 供應商設備封裝： | 68-TQFN-EP（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 32 電壓，單極 |
| 采樣率（每秒）： | * |
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32-bit command word to control the device. The com-
mand word consists of 4 control bits, 6 address bits, 14
data bits (and S1, S0 = 00), and 6 don’t-care bits. Table
6 shows the general serial data format. The control bits
control various write and read commands, as well as the
load DAC and MAC-bypass commands. Table 8 shows
the control-bit functions. The address bits select the reg-
ister(s) to update. Figure 3 shows the address functions.
The data bits control the voltage value of the DAC out-
puts. DIN data is clocked in at the falling edge of SCLK
(Figure 1).
MAX5773/MAX5774/MAX5775
32-Channel, 14-Bit, Voltage-Output
DACs with Serial Interface
______________________________________________________________________________________
19
REGISTER
CONTROL
BITS
(C3–C0)
ADDRESS
BITS
(A5–A0)
DATA BITS
(D13–D0
AND S1, S0*)
6
DON’T-
CARE
BITS
Offset
Register
1001
See Figure 3
See Table
10
XXXXXX
Gain
Register
1000
See Figure 3
See Table 9
XXXXXX
Table 7. Gain and Offset Register Input
Data Format
*
S1 = S0 = 0 for proper 14-bit operation.
4 CONTROL BITS
C3
C2
C1
C0
CONTROL-BIT DESCRIPTION
000
0
No operation (NOP). No internal registers change state. The NOP command can be passed to
DOUT depending on the state of the configuration register. Address bits A5–A0 and data bits
D13–D0 are ignored.
000
1
This instruction writes and calibrates the 14-bit input data word for gain and offset errors. Drive
LDAC low or use a software load-DAC command to update the selected DAC outputs.
001
0
Software load-DAC command. Updates the output of the selected DAC channel(s). Depending on
the address bits, this command updates one DAC output, a pair of DAC outputs, or all the DAC
outputs simultaneously. Data bits D13–D0 are ignored.
001
1
This instruction writes and calibrates the 14-bit input data word for gain and offset errors and
immediately updates the DAC outputs for the selected address.
010
0
Read command. Depending on the address bits, one of the input register values is read back
through DOUT. Data bits D13–D0 are ignored. See the Daisy-Chain Operation section.
0
1
0
1
Reserved; do not use.
0
1
0
Reserved; do not use.
011
1
MAC-bypass command. Depending on the address bits, one, two, or all DAC registers are loaded
with a 14-bit data word at DIN. The input data is not calibrated for gain and offset errors (see the
MAC-Bypass section). Selected DAC output(s) are immediately updated.
100
0
Loads D13–D0 into one or two of the gain register(s) for the selected address. The data for the
selected address is calibrated for gain error. Drive
LDAC low or use a software load-DAC
command to update the selected DAC outputs.
100
1
Loads D13–D0 into one or two of the offset register(s) for the selected address. The data for the
selected address is calibrated for offset error. Drive
LDAC low or use a software load-DAC
command to update the selected DAC outputs.
1
0
1
0
Read command. Reads one of the gain registers and presents the data at DOUT.
1
0
1
Read command. Reads one of the offset registers and presents the data at DOUT.
1
0
Write command. Loads D13–D0 into the configuration register.
1
0
1
Read command. Reads the contents of the configuration register.
1
0
Read command. Reads the DAC register for the selected address.
1
Reset instruction.
Table 8. Control-Bit Functions
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