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參數(shù)資料
| 型號： | MAX5774UTK+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 10/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT 32CH V-OUT 68-TQFN |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 設置時間： | 20µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行 |
| 轉換器數(shù)目： | 32 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-TQFN 裸露焊盤 |
| 供應商設備封裝： | 68-TQFN-EP（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 32 電壓，單極 |
| 采樣率（每秒）： | * |
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MAX5773/MAX5774/MAX5775
GAIN = 10/3 for the MAX5773/MAX5774/MAX5775.
Load-DAC (
LDAC) Input
The MAX5773/MAX5774/MAX5775 feature an active-
low LDAC input that allows the outputs (OUT_) to
update asynchronously. Keep LDAC high during nor-
mal operation (when the device is controlled only
through the serial interface). Drive LDAC low to simulta-
neously update all DAC outputs with data from their
respective input registers. Figure 2 shows the LDAC
timing with respect to OUT_.
A software command can also perform the LDAC oper-
ation. To initiate LDAC by software, set control bits
C3–C0 = 0010, address bits A5–A0 = 111111, and all
data bits to don’t care. See Table 3 for the data format.
This operation updates all DAC outputs simultaneously.
The software load-DAC command for all channels does
not affect the offset DAC.
Software MAC-Bypass
The MAX5773/MAX5774/MAX5775 feature a software
MAC-bypass command that loads data into the DAC
directly from DIN. Software MAC-bypass loads one DAC,
a pair of DACs, or all 32 DACs with a data word (D13–D0
and S1, S0) entered at DIN and the selected DAC out-
put(s) are simultaneously updated. Software MAC-
bypass bypasses gain and offset calibration, sending
the input data directly to the DAC register immediately
updating the selected DAC outputs. After executing
MAC-bypass on a channel(s), previously calibrated data
can be reloaded into the DAC by executing software
load-DAC or hardware LDAC (see Figure 4). Using soft-
ware MAC-bypass, the DAC output(s) can be set to the
ground-sense value or any arbitrary value within the DAC
output voltage range.
To activate software MAC-bypass, set control bits
C3–C0 = 0111. The address bits (A5–A0) select the
DAC(s) to be updated and the data bits (D13–D0) con-
trol the DAC output voltage value. Table 4 shows the
input data format for the software-controlled MAC-
bypass command.
Reset (
RESET)
The MAX5773/MAX5774/MAX5775 feature an active-
low RESET logic input that asynchronously sets all the
registers to code 0000h (power-up state). The serial
interface can also issue a software-reset command.
Setting the control bits C3–C0 = 1111 performs the
same function as driving the logic input RESET low.
Table 5 shows the reset data format for the software-
controlled reset command. The software reset does not
work in daisy-chain mode. Reprogram the offset DAC
after asserting a software or hardware reset.
Serial Interface
The MAX5773/MAX5774/MAX5775 allow channel updates
either individually or in pairs. This is achieved by dividing
the 32 channels into two channel banks, with 16 channels
in each bank. Channel bank 0 contains output channels
OUT0–OUT15 and channel bank 1 contains channels
OUT16–OUT31. A channel from bank 0 is paired with a
channel from bank 1 and is ordered as OUT0:OUT16,
OUT1:OUT17...OUT14:OUT30, OUT15:OUT31.
A 3-wire SPI-/QSPI-/MICROWIRE- and DSP-compatible
serial interface controls the MAX5773/MAX5774/
MAX5775. The interface requires a
32-Channel, 14-Bit, Voltage-Output
DACs with Serial Interface
18
______________________________________________________________________________________
CONTROL
BITS
ADDRESS
BITS
DATA BITS
DON’T-CARE
BITS
C3–C0
A5–A0
D13–D0 and
S1, S0*
6 Don’t-Care
Bits
1111
XXXXXX
XXXXXXXXXX
XXXX00
XXXXXX
Table 5. Reset Data Format
*
S1 = S0 = 0 for proper 14-bit operation.
CONTROL
BITS
ADDRESS
BITS
DATA BITS
DON’T-CARE
BITS
C3–C0
A5–A0
D13–D0 and
S1, S0*
6 Don’t-Care
Bits
0111
See Figure 3
D13–D0,
S1, S0*
XXXXXX
Table 4. MAC-Bypass Data Format
*
S1 = S0 = 0 for proper 14-bit operation.
CONTROL
BITS
ADDRESS
BITS
DATA BITS
6 DON’T-
CARE BITS
MSB
LSB
C3–C0
A5–A0
D13–D0 and
S1, S0*
XXXXXX
Table 6. Serial Data Format
*
S1 = S0 = 0 for proper 14-bit operation.
INPUT_
REGISTER
GAIN
OFFSET
DAC_
REGISTER
CALIBRATED
DATA REGISTER
DAC_
LDAC
+
*
MAC-BYPASS
DIN
Figure 4. MAC-Bypass Functional Diagram
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