參數(shù)資料
型號(hào)： MAX5755UTN+T
廠商： Maxim Integrated Products
文件頁數(shù)： 24/25頁
文件大小： 0K
描述： IC DAC 14BIT 32CHAN SER 56-TQFN
標(biāo)準(zhǔn)包裝： 2,500
設(shè)置時(shí)間： 20µs
位數(shù)： 14
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 32
電壓電源： 模擬和數(shù)字
工作溫度： 0°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 56-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 56-TQFN-EP（8x8）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 32 電壓，單極
采樣率（每秒）： *
MAX5753/MAX5754/MAX5755
32-Channel, 14-Bit, Voltage-Output
DACs with Serial Interface
8
_______________________________________________________________________________________
TIMING CHARACTERISTICS—DVDD = +2.7V to +5.25V
(Figures 2 and 3, AVDD = +4.75V to +5.25V, DVDD = +2.7V to +5.25V, AGND = DGND = REFGND = GS = 0, TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Serial Clock Frequency
fSCLK
025
MHz
SCLK Pulse-Width High
tCH
10
ns
SCLK Pulse-Width Low
tCL
10
ns
SCLK Fall to
CS Fall Setup Time
tSCS
10
ns
CS Fall to SCLK Fall Setup Time
tCSS
10
ns
CS Rise to SCLK Fall
tCS1
At end of cycle in SPI mode only
18
ns
SCLK Fall to
CS Rise Setup Time
tCS2
0ns
DIN to SCLK Fall Setup Time
tDS
10
ns
DIN to SCLK Fall Hold Time
tDH
2ns
SCLK Fall to DOUT Fall
tSCL
Load capacitance = 20pF (Note 9)
35
ns
SCLK Fall to DOUT Rise
tSDH
Load capacitance = 20pF (Note 9)
35
ns
CS Pulse-Width High
tCSPWH
50
ns
CS Pulse-Width Low
tCSPWL
20
ns
LDAC Pulse-Width Low
tLDAC
20
ns
CLR Pulse-Width Low
tCLR
20
ns
TIMING CHARACTERISTICS—DVDD = +4.75V to +5.25V
(Figures 2 and 3, AVDD = +4.75V to +5.25V, DVDD = +4.75V to +5.25V, AGND = DGND = REFGND = GS = 0, TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Serial Clock Frequency
fSCLK
033
MHz
SCLK Pulse-Width High
tCH
10
ns
SCLK Pulse-Width Low
tCL
10
ns
SCLK Fall to
CS Fall Setup Time
tSCS
6ns
CS Fall to SCLK Fall Setup Time
tCSS
5ns
CS Rise to SCLK Fall
tCS1
At end of cycle in SPI mode only
15
ns
SCLK Fall to
CS Rise Setup Time
tCS2
0ns
DIN to SCLK Fall Setup Time
tDS
10
ns
DIN to SCLK Fall Hold Time
tDH
2ns
SCLK Fall to DOUT Fall
tSCL
Load capacitance = 20pF
20
ns
SCLK Fall to DOUT Rise
tSDH
Load capacitance = 20pF
20
ns
CS Pulse-Width High
tCSPWH
50
ns
CS Pulse-Width Low
tCSPWL
20
ns
LDAC Pulse-Width Low
tLDAC
20
ns
CLR Pulse-Width Low
tCLR
20
ns
Note 9: The maximum clock frequency (fSCLK) is 10MHz in daisy-chain mode when DVDD < 4.75V.
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