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參數(shù)資料
| 型號： | MAX555CQK |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | DAC |
| 英文描述： | 300Msps, 12-Bit DAC with Complementary Voltage Outputs |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 0.015 us SETTLING TIME, 12-BIT DAC, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 98K |
| 代理商： | MAX555CQK |
M
300Msps, 12-Bit DAC with
Complementary Voltage Outputs
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(AV
EE
= DV
EE
= -5.2V, V
REF
= 1.000V, T
MIN
to T
MAX
= 0°C to +70°C, unless otherwise noted.) (Note 2.)
AV
EE
= DV
EE
= -5.2V
AV
EE
= DV
EE
= -5.2V
V
IL
= -1.95V
VOUT, VOUT
VOUT, VOUT
V
IH
= -0.75V
V
REF
= 1.000V, R
L
= 0
T
A
= +25°C
T
A
= +25°C
Bypass = 1, transparent mode (Notes 4, 7)
Bypass = 1, transparent mode (Notes 4, 7)
-3dB
V
REF
= 1.000V
Bypass = 0, clocked mode (Notes 4, 7)
Bypass = 0, clocked mode (Notes 4, 7)
Bypass = 0, clocked mode (Notes 4, 7)
Bypass = 1, transparent mode (Notes 4, 7)
CONDITIONS
mA
W
110
150
0.98
190
1.3
DI
EE
PD
Digital Power-Supply Current
Power Dissipation
Package Thermal Resistance,
J unction to Ambient
mA
30
46
60
AI
EE
Analog Power-Supply Current
pF
15
C
OUT
Output Capacitance
POWER SUPPLIES
49.5
50.0
50.5
R
OUT
Output Resistance
mA
19.0
20.0
21.0
I
OUT
Full-Scale Output Current
μV
-250
0
250
V
OS
Input Offset Voltage
OUTPUT PERFORMANCE
kV/V
3
20
AV
OL
Open-Loop Gain
MHz
10
BW
Multiplying Input Bandwidth
775
800
825
R
IN
Amplifier Input Resistance
ps
600
t
DD
MSBs Decode Delay
CONTROL AMPLIFIER
μA
V
V
1
2
0
I
IL
V
IH
V
IL
Input Current, Logic Low
Logic "1" Voltage
Logic "0" Voltage
DIGITAL TIMING
μA
10
200
I
IH
Input Current, Logic High
ns
2.1
t
PD1
MSBs Data-to-VOUT
Propagation Delay
ns
1.5
t
PD2
LSBs Data-to-VOUT
Propagation Delay
ns
2.0
t
PD3
Clock-to-VOUT
Propagation Delay
ns
1.8
t
HOLD
Data-to-Clock Hold Time
-1.1
-2.0
-0.75
-1.95
-1.48
ps
1
t
SU
Data-to-Clock Setup Time
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
°C/W
28
T
J A
Note 2:
All devices are 100% production tested at +25°C and are guaranteed by design for T
A
= T
MIN
to T
MAX
as specified.
Note 3:
The gain-error method of calculation is shown below:
Definition:
[V
MEASURE(FS)
- V
IDEAL(FS)
] x 100
EG(%) = ––––––––––––––––––––––––––––––––––
V
IDEAL(FS)
where FS indicates full-scale measurements.
EG Method:
EG = [(4096 / 4095) V
MEASURE
- 16(V
REF
/ R
IN
) (R
OUT
)] x 100
–––––––––––––––––––––––––––––––––––––––––––––––––– %
16(V
REF
/ R
IN
) (R
OUT
)
= [(4096 / 4095) V
MEASURE
- 1] x 100
––––––––––––––––––––––––––––––––- %
1
where: V
REF
= 1.000V, R
IN
= 800
, R
OUT
= 50
, V
MEASURE
= VOUT (FS).
Note 4:
Dynamic and timing specifications are obtained from device characterization and simulation testing and are not production tested.
Note 5:
Spurious-free dynamic range is measured from the fundamental frequency to any harmonic or non-harmonic spurs within
the bandwidth f
CLK
/2, unless otherwise specified.
Note 6:
Guaranteed by design.
Note 7:
Timing definitions are detailed in Figure 2.
Minimum data rate = DC (Note 6)
MHz
300
f
D
Data Update Rate
DIGITAL INPUTS
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