- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384687 > MAX555 (Maxim Integrated Products, Inc.) 300Msps, 12-Bit DAC with Complementary Voltage Outputs PDF資料下載
參數(shù)資料
| 型號： | MAX555 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | 300Msps, 12-Bit DAC with Complementary Voltage Outputs |
| 中文描述： | 300Msps、12位DAC，互補電壓輸出 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 98K |
| 代理商： | MAX555 |
M
300Msps, 12-Bit DAC with
Complementary Voltage Outputs
_______________________________________________________________________________________
7
T iming Information
The MAX555 features a differential ECL clock input with
selective transparent operation (BYPASS = 1). It is possi-
ble to drive the MAX555 clock single-ended if desired by
tying the CLK input to an external voltage of -1.3V (ECL
V
BB
). However, using a differential clock provides greater
noise immunity and improved dynamic performance.
In the clocked mode (BYPASS = 0), when the clock line
is low, the slave register is locked out and information
on the digital inputs is permitted to enter the master
register. The clock transition from low to high locks the
master register in its present state and ignores further
changes on the digital inputs. This transition simultane-
ously transfers the contents of the master register to the
slave register, causing the DAC output to change.
Figure 2’s timing diagram illustrates the importance of
operating the MAX555 in the clocked mode. In the trans-
parent mode (BYPASS = 1), both the master and slave
registers are transparent, and changes in input data rip-
ple directly to the output. Because the four MSBs are
decoded into 15 identical currents, there is a decode
delay for these bits that is longer than for the eight LSBs.
For the full-scale transition case shown, an intermediate
output of 1/16 full-scale occurs until the four MSBs are
properly decoded. This decode delay seriously degrades
the device’s spurious performance. In addition, skew in
the timing of the input data also directly appears at the
DAC output, further degrading high-speed performance.
MAX555 operation in the clocked mode (BYPASS = 0)
with a differential clock precludes both of these poten-
tial problems and is required for high-speed operation.
Since input data can only enter the master register
when the clock is low (while the slave register is locked
out), data-bus timing skew and the internal MSB
decode delay will not appear at the DAC output. The
DAC currents are switched only when the clock transi-
tions from low to high, after the internal data stabilizes.
Layout and Power S upplies
The MAX555 has separate pins for analog and digital
supplies. AV
EE
and DV
EE
are connected to each other
through the substrate of the IC. These potentials
should be derived from the same supply to minimize
voltage mismatch, which would cause substrate current
flow and possible latchup. Appropriate decoupling is
needed to prevent digital-section current spikes from
affecting the analog section (Figure 4).
It is recommended that a multilayer PC board be used,
containing a solid ground and power planes. All analog
VOUT
TRANSPARENT MODE
BYPASS = 1
CLOCKED MODE
BYPASS = 0
D0 D11
VOUT
D0 D11
CLK
VOUT
VOUT
t
SU
t
DD
F.S.
t
PD2
16
15
F.S.
16
1
t
HOLD
t
PD3
t
PD1
Figure 2. Timing Diagram
Table 1. Output Coding
100000000000
111111111111
-0.499756
0
-0.500000
-0.999756
011111111111
-0.500000
-0.499756
VOUT
(V)
VOUT
(V)
000000000000
000000000001
-0.999756
-0.999512
0
DIGITAL CODE
(D11–D0)
-0.000244
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX555CQK | 300Msps, 12-Bit DAC with Complementary Voltage Outputs |
| MAX560-MAX561 | +3.3V Transceiver with Wow EIA/TIA-562 Receivers Active in Shutdown |
| MAX560CAI | +3.3V Transceiver with Wow EIA/TIA-562 Receivers Active in Shutdown |
| MAX561CAI | +3.3V Transceiver with Wow EIA/TIA-562 Receivers Active in Shutdown |
| MAX561CWI | +3.3V Transceiver with Wow EIA/TIA-562 Receivers Active in Shutdown |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX5550ETE | 功能描述:數(shù)模轉(zhuǎn)換器- DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX5550ETE+ | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 10-Bit 2Ch Precision DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX5550ETE+T | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 10-Bit 2Ch Precision DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX5550ETE-T | 功能描述:數(shù)模轉(zhuǎn)換器- DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX5550EVKIT+ | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 MAX5548/50 Eval Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
發(fā)布緊急采購，3分鐘左右您將得到回復。