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參數(shù)資料
| 型號： | MAX555 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | 300Msps, 12-Bit DAC with Complementary Voltage Outputs |
| 中文描述： | 300Msps、12位DAC，互補電壓輸出 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 98K |
| 代理商： | MAX555 |
M
300Msps, 12-Bit DAC with
Complementary Voltage Outputs
_______________________________________________________________________________________
5
_______________Detailed Desc ription
Figure 1’s functional diagram shows the MAX555’s three
major divisions: a digital section, a control-amplifier sec-
tion, and a resistor-divider network. The digital section
consists of a master/slave register, decoding logic, and
current switches. The control-amplifier section includes a
control amplifier and an array of 23 current sources divid-
ed into three groups. The resistor divider scales the cur-
rents from these groups to achieve the correct binary
weighting at the output. The output of the resistor-divider
network is laser trimmed to 50
, a key feature for driving
into controlled impedance transmission lines.
The first group of current sources comprises the six
MSBs, D11–D6 (resulting in 15 identical, plus two binary
weighted currents), which are applied directly to the out-
put of the resistor-divider network. The second group,
bits D5–D3 (three binary weighted currents), is applied
to the middle of the divider network. The middle of the
network divides the current seen at the output by 8. The
third group, bits D2–D0 (three additional binary weighted
current sources), is applied to the input of the resistive
network, dividing the current seen at the output by 64.
Glitching is reduced by decoding the four MSBs into 15
identical current sources and synchronizing data with a
master/slave register at every current switch. Data bits
are transferred to the output on the positive-going edge
of the clock, with the BYPASS input asserted low. In
the asynchronous mode with the BYPASS input assert-
ed high, the latches are transparent and data is trans-
ferred to the output regardless of the clock state. All
digital inputs are ECL compatible. The clock input is
differential.
The control amplifier forces a reference current, which is
replicated in the current sources. This reference current
is nominally 1.25mA. It can be supplied by an external
current source, or by an external voltage source of
1.000V applied to the VREF input.
A reference input of V
REF
= 1.000V will produce a full-
scale output voltage of V
FS
= -1.000V, where:
V
FS
= 4096 / 4095 x VOUT (code 0)
for the VOUT output. The output coding is summarized
in Table 1.
The DAC’s control amplifier has a typical open-loop volt-
age gain of 85dB, and its gain-magnitude bandwidth is
flat up to 10MHz. When the control amplifier is not being
used for high-speed multiplying applications, it is recom-
mended that a 0.4μF capacitor be connected from LBIAS
to AV
EE
to increase control-amplifier stability and reduce
current-source noise.
_____________________Pin Desc ription
Data Words (ECL inputs)
D11(MSB)–
D0(LSB)
54, 58, 59,
60, 62, 64,
65, 67, 6,
7, 8, 9
Ladder-Bias Alternate
Compensation Output (con-
nect bypass capacitor to AV
EE
)
LBIAS
50
Analog Reference Voltage
Inputs (Kelvin connection)
VREF
38, 39
Control-Amplifier PTAT
Reference Compensation
Input (connect bypass capaci-
tor to AV
EE
)
ALTCOMPC
47
Offset Compensation Input
ROFFSET
42
Heatspreader Connections—
bypass with 0.1μF to AV
EE
PTAT-IB Reference
Compensation Output (con-
nect bypass capacitor to
AV
EE
)
HS
26, 44
Test node—must connect to
AGND
LOOPCRNT
32
Analog Reference Voltage
Center-Tap Input
VREF/2
35
-5.2V Analog Power Supplies
AV
EE
33, 34
ALTCOMPIB
28
PIN
Disables latching of data
when high (ECL input)
Data Clock (ECL input)
Data Clock Not (ECL input)
BYPASS
1
FUNCTION
NAME
CLK
CLK
2
3
-5.2V Digital Power Supplies
DV
EE
5, 55
Digital Signal Grounds
DGND
4, 56, 57,
63, 66
DAC Outputs
Ladder Grounds
VOUT
LGND
13, 14
15, 16
No Connection
N.C.
10, 11, 12,
21–25, 27,
31, 36, 37,
40, 41, 43,
45, 46, 61
DAC Output Complements
Test Node—internal test point,
do not connect
VOUT
17, 18
19, 49, 51,
52, 53, 68
Analog Signal Grounds
AGND
20, 29, 30,
48
TN
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