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參數(shù)資料
| 型號： | MAX5548ETE+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 3/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8BIT DUAL 30MA 16-TQFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 設(shè)置時(shí)間： | 30µs |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | I²C，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 16-TQFN（3x3） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電流，單極 |
| 采樣率（每秒）： | 10M |
address bits and a read/write bit (R/W). When idle, the
device continuously waits for a START condition fol-
lowed by its slave address. When the device recog-
nizes its slave address, it acquires the data and
executes the command. The first 5 bits (MSBs) of the
slave address have been factory programmed and are
always 01100. Connect A1 and A0 to VDD or GND to
program the remaining 2 bits of the slave address. Set
the least significant bit (LSB) of the address byte (R/W)
to zero to write to the MAX5548. After receiving the
address, the MAX5548 (slave) issues an acknowledge
by pulling SDA low for one clock cycle. I2C read com-
mands (R/W = 1) are not acknowledged by the
MAX5548.
Write Cycle
The write command requires 27 clock cycles. In write
mode (R/W = 0), the command/data byte that follows
the address byte controls the MAX5548 (Table 3). The
registers update on the rising edge of the 26th SCL
pulse. Prematurely aborting the write cycle does not
update the DAC. See Table 4 for a command summary.
SPI Compatibility (SPI/
I2C = VDD)
The MAX5548 is compatible with the 3-wire SPI serial
interface (Figure 6). This interface mode requires three
inputs: chip-select (CS), data clock (SCLK), and data in
(DIN). Drive CS low to enable the serial interface and
clock data synchronously into the shift register on each
SCLK rising edge.
The MAX5548 requires 16 clock cycles to clock in 6
command bits (C5–C0) and 8 data bits (D7–D0) and S1
= S0 = 0 (Figure 7). After loading data into the shift regis-
ter, drive CS high to latch the data into the appropriate
DAC register and disable the serial interface. Keep CS
low during the entire serial data stream to avoid corrup-
tion of the data. See Table 4 for a command summary.
Shutdown Mode
The MAX5548 has a software shutdown mode that
reduces the supply current to less than 1A. Shutdown
mode disables the DAC outputs. The serial interface
remains active in shutdown. This provides the flexibility
to update the registers while in shutdown. Recycling the
power supply resets the device to the default settings.
MAX5548
Dual, 8-Bit, Programmable, 30mA
High-Output-Current DAC
______________________________________________________________________________________
11
12
8
9
ACKNOWLEDGE
SCL
S
SDA
Figure 5. Acknowledge Condition
S
T
A
R
T
ADDRESS
BYTE
R/ W**
COMMAND/DATA BYTE
DATA BYTE*
S
T
O
P
Master
SDA
S
0
11
00
A
1
A0
0
C5 C4
C3
C2 C1 C0 D7 D6
D5 D4 D3 D2 D1 D0 S1** S0**
P
Slave
SDA
A
C
K
ACK
A
C
K
Table 3. Write Operation
*S1 and S0 are subbits. Set S1 and S0 to zero for proper 8-bit operation.
**Read operation not supported.
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