參數(shù)資料
型號(hào): MAX5548ETE+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 2/15頁(yè)
文件大?。?/td> 0K
描述: IC DAC 8BIT DUAL 30MA 16-TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
設(shè)置時(shí)間: 30µs
位數(shù): 8
數(shù)據(jù)接口: I²C,串行,SPI?
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 16-TQFN(3x3)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 2 電流,單極
采樣率(每秒): 10M
MAX5548
Early STOP Conditions
The MAX5548 recognizes a STOP condition at any point
during transmission except if a STOP condition occurs in
the same high pulse as a START condition (Figure 4).
This condition is not allowed in the I2C format.
Repeated START Conditions
A repeated START (Sr) condition is used when the bus
master is writing to several I2C devices and does not
want to relinquish control of the bus. The MAX5548’s
serial interface supports continuous write operations
with an Sr condition separating them.
Acknowledge Bit (ACK)
Successful data transfers are acknowledged with an
acknowledge bit (ACK). Both the master and the
MAX5548 (slave) generate acknowledge bits. To gen-
erate an acknowledge, the receiving device must pull
SDA low before the rising edge of the acknowledge-
related clock pulse (ninth pulse) and keep it low during
the high period of the clock pulse (Figure 5).
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuc-
cessful data transfer, the master should reattempt com-
munication at a later time.
Slave Address
A master initiates communication with a slave device
by issuing a START condition followed by a slave
address (see Table 3). The slave address consists of 7
Dual, 8-Bit, Programmable, 30mA
High-Output-Current DAC
10
______________________________________________________________________________________
SP
Sr
SCL
SDA
Figure 3. START and STOP Conditions
SCL
SDA
STOP
START
SCL
SDA
ILLEGAL
STOP
START
ILLEGAL EARLY STOP CONDITION
LEGAL STOP CONDITION
Figure 4. Early STOP Conditions
SCL
SDA
S
P
Sr
tSU:DAT
tHD:DAT
tRDA
tRCL
tFCL
tHIGH
tLOW
tHIGH
tLOW
tFCL
tRCL
tSU:STO
tHD:STA
tFDA
tSU:STA
Figure 2. I2C Serial-Interface Timing Diagram
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