256-Tap, Nonvolatile, I2C-Interface, Digital Potentiomet" />
參數(shù)資料
型號: MAX5418LETA+T
廠商: Maxim Integrated Products
文件頁數(shù): 4/14頁
文件大小: 0K
描述: IC POT DGTL 256-TAP I2C 8-TDFN
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1
接片: 256
電阻(歐姆): 100k
電路數(shù): 1
溫度系數(shù): 標準值 35 ppm/°C
存儲器類型: 非易失
接口: I²C(設(shè)備位址)
電源電壓: 2.7 V ~ 5.25 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-WDFN 裸露焊盤
供應商設(shè)備封裝: 8-TDFN-EP(3x3)
包裝: 標準包裝
產(chǎn)品目錄頁面: 1399 (CN2011-ZH PDF)
其它名稱: MAX5418LETA+TDKR
MAX5417/MAX5418/MAX5419
256-Tap, Nonvolatile, I2C-Interface,
Digital Potentiometers
12
______________________________________________________________________________________
ADDRESS BYTE
CONTROL BYTE
DATA BYTE
1
2345
678
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
P
SCL CYCLE
NUMBER
S
A6
A5
A4
A3
A2
A1
A0
ACK
TX
NV
V
R3
R2
R1
R0
ACK
D7
D6
D5
D4
D3
D2
D1
D0
ACK
VREG
0
1
0
1
A2
A1
A0
0
1
0
1
D7
D6
D5
D4
D3
D2
D1
D0
NVREG
0
1
0
1
A2
A1
A0
0
1
0
1
D7
D6
D5
D4
D3
D2
D1
D0
NVREGxVREG
0
1
0
1
A2
A1
A0
0
1
0
1
XX
VREGxNVREG
0
1
0
1
A2
A1
A0
0
1
0
1
0
1
XX
Table 2. Command Byte Summary
Nonvolatile Memory
The internal EEPROM consists of an 8-bit nonvolatile
register that retains the value written to it before the
device is powered down. The nonvolatile register is
programmed with the midscale value at the factory.
Power-Up
Upon power-up, the MAX5417/MAX5418/MAX5419
load the data stored in the nonvolatile memory register
into the volatile memory register, updating the wiper
position with the data stored in the nonvolatile memory
register. This initialization period takes 10s.
Standby
The MAX5417/MAX5418/MAX5419 feature a low-power
standby. When the device is not being programmed, it
goes into standby mode and power consumption is
typically 500nA.
Applications Information
The MAX5417/MAX5418/MAX5419 are intended for cir-
cuits requiring digitally controlled adjustable resis-
tance, such as LCD contrast control (where voltage
biasing adjusts the display contrast), or for programma-
ble filters with adjustable gain and/or cutoff frequency.
Positive LCD Bias Control
Figures 9 and 10 show an application where the volt-
age-divider or variable resistor is used to make an
adjustable, positive LCD bias voltage. The op amp pro-
vides buffering and gain to the resistor-divider network
made by the potentiometer (Figure 9) or to a fixed
resistor and a variable resistor (see Figure 10).
Programmable Filter
Figure 11 shows the configuration for a 1st-order pro-
grammable filter. The gain of the filter is adjusted by
R2, and the cutoff frequency is adjusted by R3. Use the
following equations to calculate the gain (G) and the
3dB cutoff frequency (fC):
G
R
f
RC
C
=+
=
××
1
2
1
23
π
VOUT
30V
5V
W
H
L
MAX5417
MAX5418
MAx5419
VOUT
30V
5V
W
H
L
MAX5417
MAX5418
MAX5419
Figure 9. Positive LCD Bias Control Using a Voltage-Divider
Figure 10. Positive LCD Bias Control Using a Variable Resistor
X = Don’t care.
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