參數(shù)資料
型號: MAX5406ETM
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 數(shù)字電位計
英文描述: Audio Processor with Pushbutton Interface
中文描述: 10K DIGITAL POTENTIOMETER, PUSH-BUTTON CONTROL INTERFACE, QCC48
封裝: 7 X 7 MM, 0.80 MM HEIGHT, TQFN-48
文件頁數(shù): 13/26頁
文件大?。?/td> 516K
代理商: MAX5406ETM
M
Audio Processor with Pushbutton Interface
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13
Pin Description (continued)
PIN
TSSOP
TQFN
NAME
FUNCTION
36
30
CBR2
Right-Channel Bass Tone Control Capacitor Terminal 2. Connect a nonpolorized capacitor between
CBR2 and CBR1 to set the bass cutoff frequency. See the
Tone Control
section for more details.
37
31
CBR1
Right-Channel Bass Tone Control Capacitor Terminal 1. Connect a capacitor between CBR1 and
CBR2 to set the bass cutoff frequency. See the
Tone Control
section for more detail.
38
32
CTR2
Right-Channel Treble Tone Control Capacitor Terminal 2. Connect a capacitor between CTR2 and
CTR1 to set the treble cutoff frequency. See the
Tone Control
section for more details.
39
33
CTR1
Right-Channel Treble Tone Control Capacitor Terminal 1. Connect a capacitor between CTR1 and
CTR2 to set the treble cutoff frequency. See the
Tone Control
section for more details.
40
34
AMBRI
Ambience Right-Channel Input. AMBRI provides the proper ambient effect at ROUT based on the
gain between LPR and AMBRI. See the
Ambience Control
section for more details.
41
35
LPR
Left Plus Right Output Signal. LPR output provides a signal that is a combination of the left and right
input signals. See the
Ambience Control
section for more details.
42
36
V
DD
Positive Analog Supply Voltage. Bypass with a 0.1μF capacitor to system analog ground.
43
37
R2_H
Right-Channel High Terminal 2. Connect the source between R2_H and R2_L for differential signal.
Connect the source to R2_H and tie R2_L to BIAS for single-ended signals.
44
38
R2_L
Right-Channel Low Terminal 2. Connect the source between R2_H and R2_L for differential signal.
Connect R2_L to BIAS for single-ended signals.
45
39
R1_L
Right-Channel Low Terminal 1. Connect the source between R1_H and R1_L for differential signal.
Connect R1_L to BIAS for single-ended signals.
46
40
R1_H
Right-Channel High Terminal 1. Connect the source between R1_H and R1_L for differential signal.
Connect the source to R1_H and tie R1_L to BIAS for single-ended signals.
47
41
CMSNS
Common-Mode Voltage Sense. Connect to V
DD
to disable the internal bias generator and drive
BIAS with external source to set output DC level.
48
42
BIAS
Internally Generated Bias Voltage. Connect CMSNS to V
SS
to enable the internally generated
V
BIAS
.
V
BIAS
= (V
DD +
V
SS
) / 2.
Connect a 0.1μF capacitor between BIAS and system analog
ground as close to the device as possible. Do not use BIAS to drive external circuitry.
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