Single, 256-Tap Volatile, I2C, Low-Voltage Linear Ta" />
參數(shù)資料
型號(hào)： MAX5395NATA+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 4/17頁(yè)
文件大?。?/td> 0K
描述： IC DGTL POT 256POS 100KOHM 8TDFN
標(biāo)準(zhǔn)包裝： 2,500
接片： 256
電阻（歐姆）： 100k
電路數(shù)： 1
溫度系數(shù)： 標(biāo)準(zhǔn)值 50 ppm/°C
存儲(chǔ)器類型： 易失
接口： I²C
電源電壓： 1.7 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： *
封裝/外殼： *
供應(yīng)商設(shè)備封裝： *
包裝： *
12
Maxim Integrated
MAX5395
Single, 256-Tap Volatile, I2C, Low-Voltage Linear
Taper Digital Potentiometer
In read mode, the master pulls down SDA during the
9th clock cycle to acknowledge receipt of data from the
MAX5395. An acknowledge is sent by the master after
each read byte to allow data transfer to continue. A not-
acknowledge is sent when the master reads the final byte
of data from the MAX5395, followed by a STOP condition.
I2C Slave Address
The slave address is defined as the seven most signifi-
cant bits (MSBs) followed by the R/W bit. See Figure 5
and Figure 6. The five most significant bits are 01010
with the 3 LSBs determined ADDR0 as shown in Table 1.
Setting the R/W bit to 1 configures the MAX5395 for read
mode. Setting the R/W bit to 0 configures the MAX5395
for write mode. The slave address is the first byte of infor-
mation sent to the MAX5395 after the START condition.
The MAX5395 has the ability to detect an unconnected
(N.C.) state on the ADDR0 input for additional address
flexibility; if disconnecting the ADDR0 input, be certain to
minimize all loading on the ADDR0 input (i.e. provide a
landing for ADDR0, but do not allow any board traces).
I2C Message Format for Writing
A master device communicates with the MAX5395 by
transmitting the proper slave address followed by com-
mand and data word. Each transmit sequence is framed
by a START or Repeated START condition and a STOP
condition as described above. Each word is 8 bits long
and is always followed by an acknowledge clock (ACK)
pulse as shown in Figure 5. The first byte contains the
address of the MAX5395 with R/W = 0 to indicate a write.
The second byte contains the command to be executed
and the third byte contains the data to be written.
I2C Message Format for Readback Operations
Each readback sequence is framed by a START or
Repeated START condition and a STOP condition. Each
word is 8 bits long and is followed by an acknowledge
clock pulse as shown in Figure 6. The first byte contains
the address of the MAX5395 with R/W = 0 to indicate a
write. The second byte contains the register that is to
be read back. There is a Repeated START condition,
followed by the device address with R/W = 1 to indicate
Figure 4. I2C Acknowledge
Figure 5. I2C Complete Write Serial Transmission
Table 1. I2C Slave Address LSBs
N.C. = No connection.
ADDR0
A1
A0
SLAVE ADDRESS
GND
0
0101000
N.C.
0
1
0101001
VDD
1
0101011
1
SCL
START
CONDITION
SDA
29
CLOCK PULSE
FOR
ACKNOWLEDGMENT
ACKNOWLEDGE
NOT ACKNOWLEDGE
01 01 0A1A0W
D D D D D D D D
AA
A
SEE REGISTER OPTIONS
SDA
START
STOP
WRITE ADDRESS
BYTE #1: I2C SLAVE ADDRESS
WRITE REGISTER
BYTE #2: REG # = N
WRITE DATA
BYTE #3: DATA BYTE B[7:0]
SCL
REG N UPDATED
ACK. GENERATED BY MAX5395L/
MAX5395M/MAX5395N
ACK. GENERATED BY I2C MASTER
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