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參數(shù)資料
| 型號： | MAX5395NATA+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 3/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL POT 256POS 100KOHM 8TDFN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 接片： | 256 |
| 電阻（歐姆）： | 100k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 50 ppm/°C |
| 存儲器類型： | 易失 |
| 接口： | I²C |
| 電源電壓： | 1.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
11
Maxim Integrated
MAX5395
Single, 256-Tap Volatile, I2C, Low-Voltage Linear
Taper Digital Potentiometer
Figure 2. I2C Timing Diagram
I2C START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A mas-
ter initiates communication by issuing a START condition.
A START condition is a high-to-low transition on SDA with
SCL high. A STOP condition is a low-to-high transition
on SDA while SCL is high (Figure 2). A START condition
from the master signals the beginning of a transmission
to the MAX5395. The master terminates transmission
and frees the bus, by issuing a STOP condition. The bus
remains active if a Repeated START condition is gener-
ated instead of a STOP condition.
I2C Early STOP and Repeated START Conditions
The MAX5395 recognizes a STOP condition at any point
during data transmission except if the STOP condition
occurs in the same high pulse as a START condition.
For proper operation, do not send a STOP condition dur-
ing the same SCL high pulse as the START condition.
Transmissions ending in an early STOP condition will not
impact the internal device settings. If the STOP occurs
during a readback byte, the transmission is terminated
and a later read mode request will begin transfer of the
requested register data from the beginning. See Figure 3.
It is possible to interrupt a transmission to a MAX5395
with a new START (Repeated START) condition (perhaps
addressing another device), which leaves the input regis-
ters with data that has not been transferred to the internal
registers. The unused data will not be stored under these
conditions. The aborted MAX5395 I2C sequence will
have no effect on the part.
I2C Acknowledge
In write mode, the acknowledge bit (ACK) is a clocked
9th bit that the MAX5395 uses to handshake receipt of
each byte of data as shown in Figure 4. The MAX5395
pulls down SDA during the entire master-generated 9th
clock pulse if the previous byte is successfully received.
Monitoring ACK allows for detection of unsuccessful
data transfers. An unsuccessful data transfer occurs if a
receiving device is busy or if a system fault has occurred.
In the event of an unsuccessful data transfer, the bus
master will retry communication.
Figure 3. I2C START(s), Repeated START(S), and STOP(S) Conditions
SDA
SCL
START
CONDITION
(S)
tLOW
tBUF
tHIGH
tHD:STA
tSU:DAT
tR
tF
tSU:STD
REPEATED
START CONDITION
(Sr)
ACKNOWLEDGE (A)
STOP CONDITION
(P)
START CONDITION
(S)
tHD-DAT
tSU:DTA
SCL
SDA
SSrP
VALID START, REPEATED START, AND STOP PULSES
PS
P
SP
P
S
INVALID START/STOP PULSE PAIRINGS-ALL WILL BE RECOGNIZED AS STARTS
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