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參數(shù)資料
| 型號： | MAX532 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Dual, Serial-Input, Voltage-Output, 12-Bit MDAC(雙通道,串行輸入,電壓輸出,12位D/A轉(zhuǎn)換器) |
| 中文描述： | 雙路、串行輸入、電壓輸出、乘法、12位DAC |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 208K |
| 代理商： | MAX532 |
M
Dual, S erial-Input,
Voltage-Output, 12-Bit MDAC
6
_______________________________________________________________________________________
______________________________________________________________Pin Desc ription
A
AGNDA
A = VOUTA, 5V/div
TIMEBASE = 2
μ
s/div
VREFA = ±10V SQUARE WAVE
LARGE-SIGNAL PULSE RESPONSE
____________________________Typic al Operating Charac teristic s (c ontinued)
(V
DD
= 15V, V
SS
= -15V, R
L
= 2k
, C
L
= 100pF, unless otherwise noted.)
PIN
1
NAME
FUNCTION
RFBA
Feedback Resistor for DACA
2
VREFA
Reference Input for DACA
3
VOUTA
Voltage Output for DACA
4
AGNDA
Analog Ground for DACA
5
AGNDB
Analog Ground for DACB
6
VOUTB
Voltage Output for DACB
7
VREFB
Reference Input for DACB
8
RFBB
Feedback Resistor for DACB
9
V
SS
Negative Supply Voltage
10
DGND
Digital Ground
11
SCLK
Serial Clock Input
Serial Data Output. Open-drain N-channel MOSFET output: requires external pull-up resis-
tor. Data on DOUT changes on the falling edge of SCLK. Serial output data is delayed 24
clock cycles from DIN.
Serial Data Input. CMOS- and TTL-compatible input. Data is clocked into DIN on the rising
edge of SCLK.
CS
must be low for data to be clocked in.
Chip-Select Input, active low. Data is shifted in and out when
CS
is low. DAC latches are
updated when
CS
is high and
LDAC
is low.
12
DOUT
13
DIN
16
V
DD
Positive Supply Voltage
15
LDAC
Asynchronous Load DAC Input, active low. DAC latches are updated when
CS
is high and
LDAC
is low.
14
CS
A
AGNDA
A = V
OUTA
, 50mV/div
TIMEBASE = 2
μ
s/div
V
REFA
= ±100mV SQUARE WAVE
SMALL-SIGNAL PULSE RESPONSE
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