參數(shù)資料
型號: MAX532
廠商: Maxim Integrated Products, Inc.
英文描述: Dual, Serial-Input, Voltage-Output, 12-Bit MDAC(雙通道,串行輸入,電壓輸出,12位D/A轉(zhuǎn)換器)
中文描述: 雙路、串行輸入、電壓輸出、乘法、12位DAC
文件頁數(shù): 11/16頁
文件大小: 208K
代理商: MAX532
With the values of t
RC
given in Table 1, t
CSS0
is always
given by t
DV
+ t
DS
. For different values of R or C, t
RC
must be calculated to determine t
CSS0
.
Additionally, the maximum clock frequency is limited to
1
f
CLK
(max) = ————————————— .
2 x (t
DO
+ t
RC
-15ns + t
DS
)
For example, with t
RC
= 15ns (5V ±10% supply with
1k
pull-up), the maximum clock frequency is 2MHz.
Digital-to-Analog S ec tion
Figure 8 shows a simplified circuit diagram for one of
the DACs and the output amplifier.
A segmented scheme is used to improve linearity,
whereby the two MSBs of the 12-bit data word are
decoded to drive the three switches, SA, SB, and SC.
The remaining ten bits drive the switches S0 through S9
in a standard R-2R ladder configuration.
Each of the switches, SA, SB, and SC, steers 1/4 of the
total reference current with the remaining 1/4 passing
through the R-2R section.
The output amplifier and feedback resistor perform the
current-to-voltage conversion, giving the following:
VOUT_ = -D x VREF_,
where _ denotes A or B, and D is the fractional representa-
tion of the digital word. (D can be set from 0 to 4095/4096.)
M
Dual, S erial-Input,
Voltage-Output, 12-Bit MDAC
______________________________________________________________________________________
11
V
PULL-UP
(V)
4.5
4.5
4.5
4.5
4.5
11.4
11.4
11.4
11.4
11.4
13.5
13.5
13.5
13.5
13.5
C (pF)
20
35
50
100
150
20
35
50
100
150
20
35
50
100
150
R
P
(k
)
1
1
1
1
1
3
3
3
3
3
3
3
3
3
3
t
RC
(ns)
15
27
38
76
114
14
25
35
71
106
12
21
29
59
88
Table 1. t
RC
Delay Times
R
R
R
2R
2R
2R
2R
2R
2R
2R
SC
SB
SA
S9
S8
S0
R/2
RFB_
VOUT_
AGND_
SHOWN FOR ALL 1s ON DAC
VREF_
Figure 8. Simplified D/A Circuit Diagram
DACA
AGNDA
V
SS
DGND
RFBA
VOUTA
V
OUT
V
IN
-12V to -15V
V
DD
VREFA
+12V to +15V
MAX532
Figure 9. Unipolar Binary Operation
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