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參數資料
| 型號： | MAX531 |
| 廠商： | Maxim Integrated Products, Inc. |
| 元件分類： | DAC |
| 英文描述： | +5V, Low-Power, Voltage-Output, Serial 12-Bit DACs(單通道,電壓輸出,12位串行D/A轉換器) |
| 中文描述： | +5V、低功耗、電壓輸出、串行12位DAC |
| 文件頁數： | 10/16頁 |
| 文件大?。?/td> | 174K |
| 代理商： | MAX531 |
M
Daisy-Chaining Devic es
The serial output, DOUT, allows cascading of two or
more DACs. The data at DIN appears at DOUT,
delayed by 16 clock cycles plus one clock width. For
low power, DOUT is a CMOS output that does not
require an external pull-up resistor. DOUT does
not
go
into a high-impedance state when CS is high. DOUT
changes on SCLK’s falling edge when CS is low. When
CS is high, DOUT remains in the state of the last data
bit.
Any number of MAX531/MAX538/MAX539 DACs can
be daisy-chained by connecting the DOUT of one
device to the DIN of the next device in the chain. For
proper timing, ensure that t
CSS0
(CS low to SCLK high)
is greater than t
DV
+ t
DS
.
Unipolar Configuration
The MAX531 is configured for a gain of 1 (0V to V
REFIN
unipolar output) by connecting BIPOFF and RFB to
VOUT (Figure 6). The converter operates from either sin-
gle or dual supplies in this configuration. See Table 1 for
the DAC-latch contents (input) vs. the analog VOUT
(output). In this range, 1LSB = V
REFIN
(2
-12
). The
MAX538 is internally configured for unipolar Gain = 1
operation.
A gain of 2 (0V to 2V
REFIN
unipolar output) is set up by
connecting BIPOFF to AGND and RFB to VOUT (Figure
7). Table 2 shows the DAC-latch contents vs. VOUT.
The MAX531 operates from either single or dual sup-
plies in this mode. In this range, 1LSB = (2)(V
REFIN
)
(2
-12
) = (V
REFIN
)(2
-11
). The MAX539 is internally con-
figured for unipolar gain = 2 operation.
Bipolar Configuration
A bipolar range is set up by connecting BIPOFF to
REFIN and RFB to VOUT, and operating from dual
(±5V) supplies (Figure 8). Table 3 shows the DAC-latch
contents (input) vs. VOUT (output). In this range,
1 LSB = V
REFIN
(2
-11
).
Four-Quadrant Multiplic ation
The MAX531 can be used as a four-quadrant multiplier
by connecting BIPOFF to REFIN and RFB to VOUT,
using (1) an offset binary digital code, (2) bipolar power
supplies, using dual power supplies, and (3) a bipolar
analog input at REFIN within the range V
SS
+ 2V to V
DD
- 2V, as shown in Figure 9.
In general, a 12-bit DAC’s output is (D) (V
REFIN)
(G),
where “G” is the gain (1 or 2) and “D” is the binary rep-
resentation of the digital input divided by 2
12
or 4,096.
This formula is precise for unipolar operation. However,
for bipolar, offset binary operation, the MSB is really a
polarity bit. No resolution is lost, as there are the same
number of steps. The output voltage, however, has
been shifted from a range of, for example, 0V to 4.096V
(G = 2) to a range of -2.048V to +2.048V.
Keep in mind that when using the DAC as a four-quad-
rant multiplier, the scale is skewed. Negative full scale
is -V
REFIN
, while positive full scale is +V
REFIN
- 1LSB.
5V, Low-Power, Voltage-Output,
S erial 12-Bit DACs
10
______________________________________________________________________________________
MAX531
CONNECT BIPOFF
TOVOUT FOR G=1,
TOAGND FOR G=2,
OR TOREFIN FOR
BIPOLAR GAIN
INVERTED
R-2R DAC
DIN
DOUT SCLK
CS
CLR
2.048V
REFIN
REFOUT
AGNDDGND
V
DD
V
SS
0.1
μ
F
+5V
0V TO-5V
33
μ
F
0.1
μ
F
2R
2R
BIPOFF
RFB
VOUT
MAX538
MAX539
INVERTED
R-2R DAC
DIN
DOUT
SCLK
CS
REFIN
AGND
+5V
V
DD
VOUT
MAX539
ONLY
0.1
μ
F
2R
2R
Figure 3a. MAX531 Typical Operating Circuit
Figure 3b. MAX538/MAX539 Typical Operating Circuit
SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.
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