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參數(shù)資料
| 型號(hào)： | MAX531 |
| 廠商： | Maxim Integrated Products, Inc. |
| 元件分類： | DAC |
| 英文描述： | +5V, Low-Power, Voltage-Output, Serial 12-Bit DACs(單通道,電壓輸出,12位串行D/A轉(zhuǎn)換器) |
| 中文描述： | +5V、低功耗、電壓輸出、串行12位DAC |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 174K |
| 代理商： | MAX531 |
Internal Reference (MAX 531 only)
The on-chip reference is lesser trimmed to generate 2.048V
at REFOUT. The output stage can source and sink current
so REFOUT can settle to the correct voltage quickly in
response to code-dependent loading changes. Typically,
source current is 5mA and sink current is 100μA.
REFOUT connects the internal reference to the R-2R DAC
ladder at REFIN. The R-2R ladder draws 50μA maximum
load current. If any other connection is made to REFOUT,
ensure that the total load current is less than 100μA to
avoid gain errors.
For applications requiring very low-noise performance,
connect a 33μF capacitor from REFOUT to AGND. If noise
is not a concern, a lower value (3.3μF min) capacitor may
be used. To reduce noise further, insert a buffered RC filter
between REFOUT and REFIN (Figure 2). The reference
bypass capacitor C
REFOUT
is still required for reference
stability. In applications not requiring the reference, con-
nect REFOUT to V
DD
or use the MAX538 or MAX539 (no
internal reference).
External Reference
An external reference in the range (V
SS
+ 2V) to (V
DD
- 2V)
may be used with the MAX531 in dual-supply operation.
With the MAX538/MAX539 or the MAX531 in single-supply
use, the reference must be positive and may not exceed
V
DD
- 2V. The reference voltage determines the DAC’s full-
scale output. The DAC input resistance is code dependent
and is minimum (40k
) at code 555hex and virtually infinite
at code 000hex. REFIN’s input capacitance is also code
dependent and has a 50pF maximum value at several
codes. Because of the code-dependent nature of refer-
ence input impedances, a high-quality, low output imped-
ance amplifier (such as the MAX480 low-power, precision
op amp) should be used.
If an upgrade to the internal reference is required, the 2.5V
MAX873A is suitable: ±15mV initial accuracy, TCV
OUT
=
7ppm/°C (max).
Logic Interface
The MAX531/MAX538/MAX539 logic inputs are designed
to be compatible with TTL or CMOS logic levels.
However, to achieve the lowest power dissipation, drive
the digital inputs with rail-to-rail CMOS logic. With TTL
logic levels, the power requirement increases by a factor
of approximately 2.
Serial Clock and Update Rate
Figure 1 shows the MAX531/MAX538/MAX539 timing. The
maximum serial clock rate is given by 1/(t
CH
+t
CL
), approxi-
mately 14MHz. The digital update rate is limited by the
chip-select period, which is 16 x (t
CH
+ t
CL
) + t
CSW
. This
equals a 1.14μs, or 877kHz, update rate. However, the
DAC settling time to 12 bits is 25μs, which may limit the
update rate to 40kHz for full-scale step transitions.
____________Applications Information
Refer to Figures 3a and 3b for typical operating connec-
tions.
Serial Interface
The MAX531/MAX538/MAX539 use a three-wire serial
interface that is compatible with SPI , QSPI
(CPOL = CPHA = 0), and Microwire standards as shown
in Figures 4 and 5. The DAC is programmed by writing two
8-bit words (see Figure 1 and the Functional Diagram. 16
bits of serial data are clocked into the DAC MSB first with
the MSB preceded by 4 fill (dummy) bits. The 4 dummy
bits are not normally needed. They are required
only
when
DACs are daisy-chained. Data is clocked in on SCLK’s ris-
ing edge while CS is low. The serial input data is held in a
16-bit serial shift register. On CS’s rising edge, the 12 least
significant bits are transferred to the DAC register and
update the DAC. With CS high, data cannot be clocked
into the MAX531/MAX538/MAX539.
The MAX531/MAX538/MAX539 inputs data in 16-bit
blocks. The SPI and Microwire interfaces output data in 8-
bit blocks, thereby requiring two write cycles to input data
to the DAC. The QSPI interface allows variable data input
from 8 to 16 bits, and can be loaded into the DAC in one
write cycle.
M
5V, Low-Power, Voltage-Output,
S erial 12-Bit DACs
_______________________________________________________________________________________
9
300
50
1
10
100
100
M
FREQUENCY (kHz)
R
150
200
250
0
0.1
1000
TOTAL
REFERERNCE
NOISE
R
S
REFOUT
C
REFOUT
C
S
TEK 7A22
C
REFOUT
= 3.3
μ
F
C
REFOUT
= 47
μ
F
SINGLE POLE ROLLOFF
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
R
Figure 2. Reference Noise vs. Frequency
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX538 | +5V, Low-Power, Voltage-Output, Serial 12-Bit DACs(單通道,電壓輸出,12位串行D/A轉(zhuǎn)換器) |
| MAX532 | Dual, Serial-Input, Voltage-Output, 12-Bit MDAC(雙通道,串行輸入,電壓輸出,12位D/A轉(zhuǎn)換器) |
| MAX5363 | Low-Cost, Low-Power, 6-Bit DACs with 3-Wire Serial Interface in SOT23 |
| MAX5363EUT-T | Low-Cost, Low-Power, 6-Bit DACs with 3-Wire Serial Interface in SOT23 |
| MAX5364 | Low-Cost, Low-Power, 6-Bit DACs with 3-Wire Serial Interface in SOT23 |
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