參數(shù)資料
型號： MAX5233EEE+
廠商： Maxim Integrated Products
文件頁數(shù)： 14/18頁
文件大?。?/td> 0K
描述： IC DAC 10BIT DUAL 5V SER 16-QSOP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 100
設(shè)置時間： 10µs
位數(shù)： 10
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-QSOP
包裝： 管件
輸出數(shù)目和類型： 2 電壓，單極
采樣率（每秒）： *
MAX5232/MAX5233
3V/5V, 10-Bit, Serial Voltage-Output Dual DACs
with Internal Reference
_______________________________________________________________________________________
5
Note 1: Accuracy is guaranteed as shown in the following table:
Note 2: Offset is measured at the code closest to 12mV.
Note 3: Temperature coefficient is determined by the box method in which the maximum
VOUT over the temperature range is
divided by
T.
Note 4: DC crosstalk is measured as follows: set DAC A to midscale, and DAC B to zero, and measure DAC A output; then change
DAC B to full scale, and measure
VOUT for DAC A. Repeat the same measurement with DAC A and DAC B interchanged.
DC crosstalk is the maximum
VOUT measured.
Note 5: Accuracy is better than 1LSB for VOUT_ = 12mV to VDD - 180mV.
Note 6: Guaranteed by design, not production tested.
Note 7: RLOAD = ∞ and digital inputs are at either VDD or DGND.
ACCURACY GUARANTEED
VDD
(V)
FROM CODE
TO CODE
3
6
1023
5
3
1023
TIMING CHARACTERISTICS—MAX5233
(VDD = +4.5V to +5.5V, VAGND = VDGND = 0V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
(Figures 1 and 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Clock Period
tCP
74
ns
SCLK Pulse Width High
tCH
30
ns
SCLK Pulse Width Low
tCL
30
ns
CS Fall to SCLK Rise Setup Time
tCSS
30
ns
SCLK Rise to
CS Rise Hold Time
tCSH
0ns
DIN Setup Time
tDS
30
ns
DIN Hold Time
tDH
0ns
CLOAD = 200pF
45
100
SCLK Rise to DOUT Valid
Propagation Delay Time
tDO1
CLOAD = 100pF
30
ns
CLOAD = 200pF
45
100
SCLK Fall to DOUT Valid
Propagation Delay Time
tDO2
CLOAD = 100pF
30
ns
SCLK Rise to
CS Fall Delay
tCS0
10
ns
CS Rise to SCLK Rise Hold Time
tCS1
30
ns
CS Pulse Width High
tCSW
75
ns
LDAC Pulse Width Low
tLDL
30
ns
CS Rise to LDAC Rise Hold Time
tCSLD
(Note 8)
40
ns
ELECTRICAL CHARACTERISTICS—MAX5232 (continued)
(VDD = +2.7V to +3.6V, VOS_ = VAGND = VDGND = 0V, RL = 5k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values
are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLIES
Power-Supply Voltage
VDD
2.7
3.6
V
Power-Supply Current (Note 7)
IDD
420
475
A
Full power-down mode
0.9
5
One DAC shutdown mode
320
360
Power-Supply Current in Power-Down
and Shutdown Modes (Note 7)
Both DACs shutdown mode
220
245
A
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