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參數(shù)資料
| 型號： | MAX5223EKA+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 10/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8BIT DUAL LP SER SOT23-8 |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1 |
| 設置時間： | 50µs |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 串行 |
| 轉換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 |
| 供應商設備封裝： | SOT-23-8 |
| 包裝： | 標準包裝 |
| 輸出數(shù)目和類型： | 2 電壓，單極 |
| 采樣率（每秒）： | * |
| 產品目錄頁面： | 1397 (CN2011-ZH PDF) |
| 其它名稱： | MAX5223EKA+TDKR |
MAX5223
Low-Power, Dual, 8-Bit, Voltage Output
Serial DAC in 8-Pin SOT23
8
_______________________________________________________________________________________
in starting with UB1 (uncommitted bit), followed by the
remaining control bits and the data byte. The least sig-
nificant bit (LSB) of the data byte (D0) is the last bit
clocked into the shift register (Figure 2).
Table 3 is an example of a 16-bit input word. It per-
forms the following functions:
80 hex (128 decimal) loaded into DAC registers
A and B.
DAC A and DAC B are active.
Table 4 shows code examples and how to calculate
their corresponding outputs.
*Clocked in last
**Clocked in first
Uncommitted Bit 1
UB1**
Uncommitted Bit 2
UB2
Uncommitted Bit 3
UB3
Shutdown, Active-High
SB
Shutdown, Active-High
SA
Uncommitted Bit 4
UB4
Load Reg DAC B, Active-High
LB
Load Reg DAC A, Active-High
LA
DAC Data Bit 7 (MSB)
D7
DAC Data Bit 6
D6
DAC Data Bit 5
D5
DAC Data Bit 4
D4
DAC Data Bit 3
D3
DAC Data Bit 2
D2
DAC Data Bit 1
D1
DAC Data Bit 0 (LSB)
D0*
Table 1. Input Shift Register
DIN
SCLK
CS
UB1 UB2 UB3
SB
SA
UB4
LB
LA
D7
D6
D5
D4
D3
D2
D1
D0
OPTIONAL
(CONTROL BYTE)
(DATA BYTE)
INSTRUCTION
EXECUTED
Figure 2. 3-Wire Serial-Interface Timing Diagram
DATA
BITS
CONTROL
BITS
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