參數(shù)資料
型號(hào): MAX5222EKA+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 11/12頁(yè)
文件大?。?/td> 0K
描述: IC DAC 8BIT DUAL BUFF SOT23-8
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
設(shè)置時(shí)間: 10µs
位數(shù): 8
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: SOT-23-8
供應(yīng)商設(shè)備封裝: SOT-23-8
包裝: 標(biāo)準(zhǔn)包裝
輸出數(shù)目和類(lèi)型: 2 電壓,單極
采樣率(每秒): *
產(chǎn)品目錄頁(yè)面: 1397 (CN2011-ZH PDF)
其它名稱(chēng): MAX5222EKA+TDKR
MAX5222
Dual, 8-Bit, Voltage-Output
Serial DAC in 8-Pin SOT23
8
_______________________________________________________________________________________
Figure 1. DAC Simplified Circuit Diagram
2R
RR
R
REF
GND
OUT
SHOWN FOR ALL 1s ON DAC
Table 1. Input Shift Register
Serial Interface
An active-low chip select (
C
S
) enables the shift register
to receive data from the serial data input. Data is
clocked into the shift register on every rising edge of
the serial clock signal (SCLK). The clock frequency can
be as high as 25MHz.
Data is sent most significant bit (MSB) first and can be
transmitted in one 16-bit word. The write cycle can be
segmented when
C
S
is kept active (low) to allow, for
example, two 8-bit-wide transfers. After clocking all 16
bits into the input shift register, the rising edge of
C
S
updates the DAC outputs and the shutdown status.
Because of their single buffered structure, DACs cannot
be simultaneously updated to different digital values.
Serial-Input Data Format and Control Codes
Table 2 lists the serial-input data format. The 16-bit
input word consists of an 8-bit control byte and an 8-bit
data byte. The 8-bit control byte is not decoded inter-
nally. Every control bit performs one function. Data is
clocked in starting with UB1 (uncommitted bit), followed
by the remaining control bits and the data byte. The
least significant bit (LSB) of the data byte (B0) is the
last bit clocked into the shift register (Figure 2).
Table 3 is an example of a 16-bit input word. It per-
forms the following functions:
80 hex (128 decimal) loaded into DAC registers
A and B.
DAC A and DAC B are active.
*Clocked in last.
**Clocked in first.
Uncommitted Bit 1
UB1**
Uncommitted Bit 2
UB2
Uncommitted Bit 3
UB3
Shut Down, Active High
SB
Shut Down, Active High
SA
Uncommitted Bit 4
UB4
Load Reg DAC B, Active High
LB
Load Reg DAC A, Active High
LA
DAC Data Bit 7 (MSB)
B7
DAC Data Bit 6
B6
DAC Data Bit 5
B5
DAC Data Bit 4
B4
DAC Data Bit 3
B3
DAC Data Bit 2
B2
DAC Data Bit 1
B1
DAC Data Bit 0 (LSB)
B0*
DATA
BITS
CONTROL
BITS
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