參數(shù)資料
型號(hào): MAX5222EKA+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 10/12頁(yè)
文件大小: 0K
描述: IC DAC 8BIT DUAL BUFF SOT23-8
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
設(shè)置時(shí)間: 10µs
位數(shù): 8
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: SOT-23-8
供應(yīng)商設(shè)備封裝: SOT-23-8
包裝: 標(biāo)準(zhǔn)包裝
輸出數(shù)目和類型: 2 電壓,單極
采樣率(每秒): *
產(chǎn)品目錄頁(yè)面: 1397 (CN2011-ZH PDF)
其它名稱: MAX5222EKA+TDKR
MAX5222
Dual, 8-Bit, Voltage-Output
Serial DAC in 8-Pin SOT23
_______________________________________________________________________________________
7
Detailed Description
Analog Section
The MAX5222 contains two 8-bit, voltage-output DACs.
The DACs are “inverted” R-2R ladder networks using
complementary switches that convert 8-bit digital
inputs into equivalent analog output voltages in propor-
tion to the applied reference voltage.
The MAX5222 has one reference input that is shared
by DAC A and DAC B. The device includes output
buffer amplifiers for both DACs and input logic for sim-
ple microprocessor (P) and CMOS interfaces. The
power-supply range is from +5.5V down to +2.7V.
Reference Input and DAC Output Range
The voltage at REF sets the full-scale output of the
DACs. The input impedance of the REF input is code
dependent. The lowest value, approximately 8k
,
occurs when the input code is 01010101 (55hex). The
maximum value of infinity occurs when the input code
is zero.
In shutdown mode, the selected DAC output is set to
zero, while the value stored in the DAC register remains
unchanged. This removes the load from the reference
input to save power. Bringing the MAX5222 out of shut-
down mode restores the DAC output voltage. Because
the input resistance at REF is code dependent, the
DAC’s reference source should have an output imped-
ance of no more than 5
. The input capacitance at the
REF pin is also code dependent and typically does not
exceed 25pF.
The reference voltage on REF can range anywhere from
GND to VDD. See the Output Buffer Amplifier section for
more information.
Figure 1 is the DAC simplified circuit diagram.
Output Buffer Amplifiers
DAC A and DAC B voltage outputs are internally
buffered. The buffer amplifiers have a Rail-to-Rail
(GND to VDD) output voltage range.
Both DAC output amplifiers can source and sink up to
1mA of current. See the INL vs. Digital Code graph in
the Typical Operating Characteristics. The amplifiers
are unity-gain stable with a capacitive load of 100pF or
smaller. The slew rate is typically 1V/s.
Shutdown Mode
When programmed to shutdown mode, the outputs of
DAC A and DAC B are passively pulled to GND with a
series 5k
resistor. In shutdown mode, the REF input is
high impedance (2M
typical) to conserve current
drain from the system reference; therefore, the system
reference does not have to be powered down.
Coming out of shutdown, the DAC outputs return to the
values kept in the registers. The recovery time is equiv-
alent to the DAC settling time.
______________________________________________________________Pin Description
NAME
FUNCTION
1
C
S
Chip Select, Active Low. Enables data to be shifted into the 16-bit shift register. Programming commands
are executed at the rising edge of
C
S
.
2
GND
Ground
PIN
3
VDD
Positive Power Supply (+2.7V to +5.5V). Bypass with 0.22F to GND.
4
SCLK
Serial Clock Input. Data is clocked in on the rising edge of SCLK.
8
DIN
Serial Data Input of the 16-bit Shift Register. Data is clocked into the register on the rising edge of SCLK.
7
REF
Reference Input for DAC A and DAC B
6
OUTB
DAC B Output Voltage (Buffered)
5
OUTA
DAC A Output Voltage (Buffered)
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
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