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M
Dual-Phase, Parallelable, Average-Current-Mode
Controllers
24
______________________________________________________________________________________
The allowable deviation of the output voltage during the
fast transient load dictates the output capacitance and
ESR. The output capacitors supply the load step until
the controller responds with a greater duty cycle. The
response time (t
RESPONSE
) depends on the closed-loop
bandwidth of the converter. The resistive drop across
the capacitor ESR and capacitor discharge causes a
voltage drop during a step load. Use a combination of
SP polymer and ceramic capacitors for better transient
load and ripple/noise performance.
Keep the maximum output voltage deviation less than
or equal to the adaptive voltage-positioning window
(
V
OUT
). Assume 50% contribution each from the out-
put capacitance discharge and the ESR drop. Use the
following equations to calculate the required ESR and
capacitance value:
where I
STEP
is the load step and t
RESPONSE
is the
response time of the controller. Controller response
time depends on the control-loop bandwidth.
Current Limit
The average-current-mode control technique of the
MAX5038A/MAX5041A accurately limits the maximum
output current per phase. The MAX5038A/MAX5041A
sense the voltage across the sense resistor and limit
the peak inductor current (I
L-PK
) accordingly. The ON
cycle terminates when the current-sense voltage reach-
es 45mV (min). Use the following equation to calculate
maximum current-sense resistor value:
=
0 045
where PD
R
is the power dissipation in sense resistors.
Select 5% lower value of R
SENSE
to compensate for any
parasitics associated with the PC board. Also, select a
noninductive resistor with the appropriate wattage rating.
Reverse Current Limit
The MAX5038A/MAX5041A limit the reverse current in
the case that V
BUS
is higher than the preset output volt-
age setting.
Calculate the maximum reverse current based on V
CLR
,
the reverse current-limit threshold, and the current-
sense resistor:
Compensation
The main control loop consists of an inner current loop
and an outer voltage loop. The MAX5038A/MAX5041A
use an average-current-mode control scheme to regu-
late the output voltage (Figures 3a and 3b). I
PHASE1
and
I
PHASE2
are the inner average current loops. The VEA
output provides the controlling voltage for these current
sources. The inner current loop absorbs the inductor
pole reducing the order of the outer voltage loop to that
of a single-pole system.
A resistive feedback network around the VEA provides
the best possible response, since there are no capaci-
tors to charge and discharge during large-signal excur-
sions, R
F
and R
IN
determine the VEA gain. Use the
following equation to calculate the value for R
F
:
where G
C
is the current-loop transconductance and N
is the number of phases.
When designing the current-control loop ensure that the
inductor downslope (when it becomes an upslope at the
CEA output) does not exceed the ramp slope. This is a
necessary condition to avoid subharmonic oscillations
similar to those in peak-current-mode control with insuf-
ficient slope compensation. Use the following equation
to calculate the resistor R
CF
:
For example, the maximum R
CF
is 12k
for R
SENSE
=
1.35m
.
R
f
L
V
R
CF
SW
OUT
SENSE
≤
×
× ×
×
2
10
2
G
R
C
S
=
0 05
.
R
I
R
N G
V
F
OUT
IN
OUT
C
=
×
×
I
V
R
REVERSE
CLR
SENSE
=
×
2
PD
R
R
SENSE
=
2 5 10
3
.
R
I
N
SENSE
OUT
.
C
I
t
V
OUT
STEP
RESPONSE
Q
=
×
ESR
V
I
OUT
ESR
STEP
=
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)